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authorBill Schmidt <wschmidt@linux.vnet.ibm.com>2012-10-11 15:38:20 +0000
committerBill Schmidt <wschmidt@linux.vnet.ibm.com>2012-10-11 15:38:20 +0000
commit22162470ba127c626e674b0fdc90456c69ffd2cd (patch)
treea969518839e091a6e43175592d1e4079678a4499 /llvm/lib/Target/PowerPC/PPCISelLowering.cpp
parent6be23ce8214faac1c0bbba82860c85427fc6479f (diff)
downloadbcm5719-llvm-22162470ba127c626e674b0fdc90456c69ffd2cd.tar.gz
bcm5719-llvm-22162470ba127c626e674b0fdc90456c69ffd2cd.zip
This patch addresses PR13947.
For function calls on the 64-bit PowerPC SVR4 target, each parameter is mapped to as many doublewords in the parameter save area as necessary to hold the parameter. The first 13 non-varargs floating-point values are passed in registers; any additional floating-point parameters are passed in the parameter save area. A single-precision floating-point parameter (32 bits) must be mapped to the second (rightmost, low-order) word of its assigned doubleword slot. Currently LLVM violates this ABI requirement by mapping such a parameter to the first (leftmost, high-order) word of its assigned doubleword slot. This is internally self-consistent but will not interoperate correctly with libraries compiled with an ABI-compliant compiler. This patch corrects the problem by adjusting the parameter addressing on both sides of the calling convention. llvm-svn: 165714
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 64bbcdfa94e..660bfb45f82 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -2142,6 +2142,7 @@ PPCTargetLowering::LowerFormalArguments_64SVR4(
++FPR_idx;
} else {
needsLoad = true;
+ ArgSize = PtrByteSize;
}
ArgOffset += 8;
@@ -3786,6 +3787,13 @@ PPCTargetLowering::LowerCall_Darwin_Or_64SVR4(SDValue Chain, SDValue Callee,
++GPR_idx;
}
} else {
+ // Single-precision floating-point values are mapped to the
+ // second (rightmost) word of the stack doubleword.
+ if (Arg.getValueType() == MVT::f32 && isPPC64 && isSVR4ABI) {
+ SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
+ PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
+ }
+
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
isPPC64, isTailCall, false, MemOpChains,
TailCallArguments, dl);
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