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* Simplify lowering and selection of exception ops.Jim Laskey2007-02-221-34/+15
| | | | llvm-svn: 34488
* Support to provide exception and selector registers.Jim Laskey2007-02-211-0/+28
| | | | llvm-svn: 34482
* Fix ixaddrs as well, allowing ppc64 to compile to:Chris Lattner2007-02-171-17/+22
| | | | | | | | | | | | | | | | | | | | | _test2: li r2, 0 lis r3, 1 std r2, 9024(r3) blr instead of: _test2: lis r2, 1 li r3, 0 ori r2, r2, 9024 std r3, 0(r2) blr This implements CodeGen/PowerPC/LargeAbsoluteAddr.ll:test2 llvm-svn: 34373
* Compile test/CodeGen/PowerPC/LargeAbsoluteAddr.ll to:Chris Lattner2007-02-171-5/+9
| | | | | | | | | | | | | | | | | | | _test: lis r2, 743 li r3, 0 stw r3, 32751(r2) blr instead of: _test: li r2, 0 stw r2, 32751(48693248) blr Implement support for ppc64 as well, allowing it to produce better code. llvm-svn: 34371
* Finish off bug 680, allowing targets to custom lower frame and returnNate Begeman2007-01-291-0/+4
| | | | | | address nodes. llvm-svn: 33636
* Propagate changes from my local tree. This patch includes:Anton Korobeynikov2007-01-281-3/+3
| | | | | | | | | | | | | | | | | | | | | | 1. New parameter attribute called 'inreg'. It has meaning "place this parameter in registers, if possible". This is some generalization of gcc's regparm(n) attribute. It's currently used only in X86-32 backend. 2. Completely rewritten CC handling/lowering code inside X86 backend. Merged stdcall + c CCs and fastcall + fast CC. 3. Dropped CSRET CC. We cannot add struct return variant for each target-specific CC (e.g. stdcall + csretcc and so on). 4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in on first attribute has meaning 'This is hidden pointer to structure return. Handle it gently'. 5. Fixed small bug in llvm-extract + add new feature to FunctionExtraction pass, which relinks all internal-linkaged callees from deleted function to external linkage. This will allow further linking everything together. NOTEs: 1. Documentation will be updated soon. 2. llvm-upgrade should be improved to translate csret => sret. Before this, there will be some unexpected test fails. llvm-svn: 33597
* Make LABEL a builtin opcode.Jim Laskey2007-01-261-1/+1
| | | | llvm-svn: 33537
* setSetCCIsExpensive is gone.Evan Cheng2007-01-051-2/+0
| | | | llvm-svn: 32941
* Provide support for FP_TO_UINT.Jim Laskey2006-12-151-1/+3
| | | | llvm-svn: 32599
* Another step forward in PPC64 JIT support: we now no-longer need stubsChris Lattner2006-12-111-2/+1
| | | | | | | | | | emitted for external globals in PPC64-JIT-PIC mode (which is good because we didn't handle them before!). This also fixes a bug handling the picbase delta, which we would get wrong in some cases. llvm-svn: 32451
* Missing opcode.Jim Laskey2006-12-111-0/+1
| | | | llvm-svn: 32439
* Cleaned setjmp/longjmp lowering interfaces. Now we're producing rightAnton Korobeynikov2006-12-101-1/+2
| | | | | | | code (both asm & cbe) for Mingw32 target. Removed autoconf checks for underscored versions of setjmp/longjmp. llvm-svn: 32415
* Fix i64 uint_to_fp on ppc64Chris Lattner2006-12-071-1/+2
| | | | llvm-svn: 32297
* Restoration of the stack pointer after a deallocation of a alloca was notJim Laskey2006-12-041-1/+28
| | | | | | updating the SP link. llvm-svn: 32202
* 1. In ppc64 mode we need only use one GPR.Jim Laskey2006-12-011-1/+7
| | | | | | 2. Float values need to be promoted to double when they are vararg. llvm-svn: 32074
* Fix the CodeGen/PowerPC/vec_constants.ll regression.Chris Lattner2006-12-011-6/+9
| | | | llvm-svn: 32057
* Fix bug codegen'ing FP constant vectors with integer splats. Make sure theChris Lattner2006-11-291-14/+22
| | | | | | | created intrinsics have the right integer types. This fixes PowerPC/2006-11-29-AltivecFPSplat.ll llvm-svn: 32024
* Offset for load of 32-bit arg in 64-bit world was incorrect.Jim Laskey2006-11-291-1/+4
| | | | llvm-svn: 32019
* Remove debug code.Jim Laskey2006-11-281-2/+0
| | | | llvm-svn: 31970
* 32-bit int space was not accounted for properly in lowerCall.Jim Laskey2006-11-281-3/+8
| | | | llvm-svn: 31966
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-2/+3
| | | | | | of opcode and number of operands. llvm-svn: 31947
* on ppc64, float arguments take 8-byte stack slots not 4-byte stack slots.Chris Lattner2006-11-181-3/+8
| | | | | | Also, valist should create a pointer RC reg class value, not a GPRC value. llvm-svn: 31840
* convert PPC::BCC to use the 'pred' operand instead of separate predicateChris Lattner2006-11-171-2/+2
| | | | | | | | value and CR reg #. This requires swapping the order of these everywhere that touches BCC and requires us to write custom matching logic for PPCcondbranch :( llvm-svn: 31835
* rename PPC::COND_BRANCH to PPC::BCCChris Lattner2006-11-171-1/+1
| | | | llvm-svn: 31834
* start using PPC predicates more consistently.Chris Lattner2006-11-171-7/+9
| | | | llvm-svn: 31833
* This is a general clean up of the PowerPC ABI. Address several problems andJim Laskey2006-11-161-16/+59
| | | | | | | | | bugs including making sure that the TOS links back to the previous frame, that the maximum call frame size is not included twice when using frame pointers, no longer growing the frame on calls, double storing of SP and a cleaner/faster dynamic alloca. llvm-svn: 31792
* fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memriChris Lattner2006-11-151-8/+17
| | | | | | addrmodes. llvm-svn: 31757
* lower "X = seteq Y, Z" to '(shr (ctlz (xor Y, Z)), 5)' instead ofChris Lattner2006-11-141-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | '(shr (ctlz (sub Y, Z)), 5)'. The use of xor better exposes the operation to bit-twiddling logic in the dag combiner. For example, this: typedef struct { unsigned prefix : 4; unsigned code : 4; unsigned unsigned_p : 4; } tree_common; int foo(tree_common *a, tree_common *b) { return a->code == b->code; } Now compiles to: _foo: lwz r2, 0(r4) lwz r3, 0(r3) xor r2, r3, r2 rlwinm r2, r2, 28, 28, 31 cntlzw r2, r2 srwi r3, r2, 5 blr instead of: _foo: lbz r2, 3(r4) lbz r3, 3(r3) srwi r2, r2, 4 srwi r3, r3, 4 subf r2, r2, r3 cntlzw r2, r2 srwi r3, r2, 5 blr saving a cycle. llvm-svn: 31725
* minor tweaks, reject vector preinc.Chris Lattner2006-11-141-4/+9
| | | | llvm-svn: 31717
* ppc64 doesn't have lwau, don't attempt to form it.Chris Lattner2006-11-111-3/+9
| | | | llvm-svn: 31656
* implement preinc support for r+i loads on ppc64Chris Lattner2006-11-101-1/+10
| | | | llvm-svn: 31654
* add an initial cut at preinc loads for ppc32. This is broken for ppc64Chris Lattner2006-11-101-13/+14
| | | | | | | | | (because the 64-bit reg target versions aren't implemented yet), doesn't support r+r addr modes, and doesn't handle stores, but it works otherwise. :) This is disabled unless -enable-ppc-preinc is passed to llc for now. llvm-svn: 31621
* PPC supports i32 / i64 pre-inc load / store.Evan Cheng2006-11-091-0/+6
| | | | llvm-svn: 31599
* Rename ISD::MemOpAddrMode to ISD::MemIndexedModeEvan Cheng2006-11-091-1/+1
| | | | llvm-svn: 31595
* Refactor all the addressing mode selection stuff into the isel loweringChris Lattner2006-11-081-0/+279
| | | | | | class, where it can be used for preinc formation. llvm-svn: 31536
* For PR786:Reid Spencer2006-11-021-2/+0
| | | | | | | | | | Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting fall out by removing unused variables. Remaining warnings have to do with unused functions (I didn't want to delete code without review) and unused variables in generated code. Maintainers should clean up the remaining issues when they see them. All changes pass DejaGnu tests and Olden. llvm-svn: 31380
* Implement the getRegForInlineAsmConstraint method for PPC. With recentChris Lattner2006-11-021-52/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sdisel changes, this eliminates a ton of copies around common inline asms. For example: int test2(int Y, int X) { asm("foo %0, %1" : "=r"(X): "r"(X)); return X; } now compiles to: _test2: foo r3, r4 blr instead of: _test2: mr r2, r4 foo r2, r2 mr r3, r2 blr GCC produces: _test2: foo r4, r4 mr r3,r4 blr llvm-svn: 31367
* Change the prototype for TargetLowering::isOperandValidForConstraintChris Lattner2006-10-311-11/+18
| | | | llvm-svn: 31318
* All targets expand BR_JT for now.Evan Cheng2006-10-301-0/+2
| | | | llvm-svn: 31294
* set the ppc64 stack pointer right, dynamic alloca now works for ppc64Chris Lattner2006-10-181-1/+5
| | | | llvm-svn: 31028
* Expand alloca for ppc64Chris Lattner2006-10-181-1/+2
| | | | llvm-svn: 31027
* Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.Evan Cheng2006-10-131-13/+11
| | | | llvm-svn: 30945
* Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.Evan Cheng2006-10-091-14/+13
| | | | llvm-svn: 30844
* Make use of getStore().Evan Cheng2006-10-051-13/+11
| | | | llvm-svn: 30759
* Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add anEvan Cheng2006-10-041-5/+5
| | | | | | extra operand to LOADX to specify the exact value extension type. llvm-svn: 30714
* Legalize is no longer limited to cleverness with just constant shift amounts.Chris Lattner2006-09-201-41/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow it to be clever when possible and fall back to the gross code when needed. This allows us to compile: long long foo1(long long X, int C) { return X << (C|32); } long long foo2(long long X, int C) { return X << (C&~32); } to: _foo1: rlwinm r2, r5, 0, 27, 31 slw r3, r4, r2 li r4, 0 blr .globl _foo2 .align 4 _foo2: rlwinm r2, r5, 0, 27, 25 subfic r5, r2, 32 slw r3, r3, r2 srw r5, r4, r5 or r3, r3, r5 slw r4, r4, r2 blr instead of: _foo1: ori r2, r5, 32 subfic r5, r2, 32 addi r6, r2, -32 srw r5, r4, r5 slw r3, r3, r2 slw r6, r4, r6 or r3, r3, r5 slw r4, r4, r2 or r3, r3, r6 blr .globl _foo2 .align 4 _foo2: rlwinm r2, r5, 0, 27, 25 subfic r5, r2, 32 addi r6, r2, -32 srw r5, r4, r5 slw r3, r3, r2 slw r6, r4, r6 or r3, r3, r5 slw r4, r4, r2 or r3, r3, r6 blr llvm-svn: 30507
* Fold the PPCISD shifts when presented with 0 inputs. This occurs for codeChris Lattner2006-09-191-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | like: long long test(long long X, int Y) { return 1ULL << Y; } long long test2(long long X, int Y) { return -1LL << Y; } which we used to compile to: _test: li r2, 1 subfic r3, r5, 32 li r4, 0 addi r6, r5, -32 srw r3, r2, r3 slw r4, r4, r5 slw r6, r2, r6 or r3, r4, r3 slw r4, r2, r5 or r3, r3, r6 blr _test2: li r2, -1 subfic r3, r5, 32 addi r6, r5, -32 srw r3, r2, r3 slw r4, r2, r5 slw r2, r2, r6 or r3, r4, r3 or r3, r3, r2 blr Now we produce: _test: li r2, 1 addi r3, r5, -32 subfic r4, r5, 32 slw r3, r2, r3 srw r4, r2, r4 or r3, r4, r3 slw r4, r2, r5 blr _test2: li r2, -1 subfic r3, r5, 32 addi r6, r5, -32 srw r3, r2, r3 slw r4, r2, r5 slw r2, r2, r6 or r3, r4, r3 or r3, r3, r2 blr llvm-svn: 30479
* Reflects MachineConstantPoolEntry changes.Evan Cheng2006-09-121-2/+2
| | | | llvm-svn: 30279
* For PR387:Reid Spencer2006-08-281-0/+4
| | | | | | | Close out this long standing bug by removing the remaining overloaded virtual functions in LLVM. The -Woverloaded-virtual option is now turned on. llvm-svn: 29934
* Fix a bug in a recent refactoring that broke a bunch of stuff.Chris Lattner2006-08-121-1/+1
| | | | llvm-svn: 29649
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