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| author | Chris Lattner <sabre@nondot.org> | 2006-11-17 22:37:34 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-11-17 22:37:34 +0000 |
| commit | be9377a1e339bdbd76e8016e17271909822ec94f (patch) | |
| tree | 6fe958e5ba62b1019108e6d1a0d5ce234bbdd981 /llvm/lib/Target/PowerPC/PPCISelLowering.cpp | |
| parent | e0263794f4bbd004d6b361c7fa6767b8be1b2feb (diff) | |
| download | bcm5719-llvm-be9377a1e339bdbd76e8016e17271909822ec94f.tar.gz bcm5719-llvm-be9377a1e339bdbd76e8016e17271909822ec94f.zip | |
convert PPC::BCC to use the 'pred' operand instead of separate predicate
value and CR reg #. This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(
llvm-svn: 31835
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index a836c5fdbad..e96550085a1 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2614,7 +2614,7 @@ PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); unsigned SelectPred = MI->getOperand(4).getImm(); BuildMI(BB, PPC::BCC, 3) - .addReg(MI->getOperand(1).getReg()).addImm(SelectPred).addMBB(sinkMBB); + .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); MachineFunction *F = BB->getParent(); F->getBasicBlockList().insert(It, copy0MBB); F->getBasicBlockList().insert(It, sinkMBB); @@ -2890,8 +2890,8 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, } return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), - DAG.getRegister(PPC::CR6, MVT::i32), DAG.getConstant(CompOpc, MVT::i32), + DAG.getRegister(PPC::CR6, MVT::i32), N->getOperand(4), CompNode.getValue(1)); } break; |
