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path: root/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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* Autogen fselChris Lattner2005-10-251-12/+0
| | | | llvm-svn: 23987
* Autogen a few new ppc-specific nodesChris Lattner2005-10-251-12/+0
| | | | llvm-svn: 23985
* The dag isel generator generates this nowChris Lattner2005-10-251-32/+0
| | | | llvm-svn: 23984
* Be a bit more paranoid about calling SelectNodeToChris Lattner2005-10-251-7/+11
| | | | llvm-svn: 23982
* Fix a couple of minor bugs. The first fixes povray, the second fixes thingsChris Lattner2005-10-251-3/+9
| | | | | | if the dag combiner isn't run llvm-svn: 23981
* Instead of aborting if not a case we can handle specially, break out andChris Lattner2005-10-211-54/+52
| | | | | | | | let the generic code handle it. This fixes CodeGen/Generic/2005-10-21-longlonggtu.ll on ppc. also, reindent this code llvm-svn: 23874
* Invert the TargetLowering flag that controls divide by consant expansion.Nate Begeman2005-10-211-0/+5
| | | | | | | | | | Add a new flag to TargetLowering indicating if the target has really cheap signed division by powers of two, make ppc use it. This will probably go away in the future. Implement some more ISD::SDIV folds in the dag combiner Remove now dead code in the x86 backend. llvm-svn: 23853
* Move the target constant divide optimization up into the dag combiner, soNate Begeman2005-10-201-160/+0
| | | | | | | that the nodes can be folded with other nodes, and we can not duplicate code in every backend. Alpha will probably want this too. llvm-svn: 23835
* Write patterns for the various shl and srl patterns that don't involveNate Begeman2005-10-191-33/+10
| | | | | | doing something clever. llvm-svn: 23824
* Convert these cases to patternsChris Lattner2005-10-191-28/+0
| | | | llvm-svn: 23811
* Woo, it kinda works. We now generate this atrociously bad, but correct,Nate Begeman2005-10-191-21/+38
| | | | | | | | | | | | | | | | | | | | | | | code for long long foo(long long a, long long b) { return a + b; } _foo: or r2, r3, r3 or r3, r4, r4 or r4, r5, r5 or r5, r6, r6 rldicr r2, r2, 32, 31 rldicl r3, r3, 0, 32 rldicr r4, r4, 32, 31 rldicl r5, r5, 0, 32 or r2, r3, r2 or r3, r5, r4 add r4, r3, r2 rldicl r2, r4, 32, 32 or r4, r4, r4 or r3, r2, r2 blr llvm-svn: 23809
* Make a new reg class for 64 bit regs that aliases the 32 bit regs. ThisNate Begeman2005-10-191-3/+21
| | | | | | | | | | | will have to tide us over until we get real subreg support, but it prevents the PrologEpilogInserter from spilling 8 byte GPRs on a G4 processor. Add some initial support for TRUNCATE and ANY_EXTEND, but they don't currently work due to issues with ScheduleDAG. Something wll have to be figured out. llvm-svn: 23803
* Add the ability to lower return instructions to TargetLowering. ThisNate Begeman2005-10-181-5/+16
| | | | | | | allows us to lower legal return types to something else, to meet ABI requirements (such as that i64 be returned in two i32 regs on Darwin/ppc). llvm-svn: 23802
* First bits of 64 bit PowerPC stuff, currently disabled. A lot of this isNate Begeman2005-10-181-22/+29
| | | | | | purely mechanical. llvm-svn: 23778
* More PPC32 -> PPC changes, as well as merging some classes that wereNate Begeman2005-10-161-4/+4
| | | | | | redundant after the change. llvm-svn: 23759
* Remove some dead code: the ORI/ORIS cases are autogen'd. This makesChris Lattner2005-10-151-42/+1
| | | | | | SelectIntImmediateExpr dead. llvm-svn: 23753
* These instructions are now autogeneratedChris Lattner2005-10-151-34/+0
| | | | llvm-svn: 23751
* remove dead codeChris Lattner2005-10-151-8/+3
| | | | llvm-svn: 23749
* Rename PPC32*.h to PPC*.hChris Lattner2005-10-141-2/+2
| | | | | | This completes the grand PPC file renaming llvm-svn: 23745
* Rename PowerPC*.h to PPC*.hChris Lattner2005-10-141-1/+1
| | | | llvm-svn: 23743
* Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.tdChris Lattner2005-10-141-1/+1
| | | | llvm-svn: 23738
* These are now autogeneratedChris Lattner2005-10-141-12/+0
| | | | llvm-svn: 23731
* Disable formation of rlwinm instructions from SRA bases. This fixesChris Lattner2005-10-091-2/+2
| | | | | | | | | the 177.mesa failure from last night, and fixes the CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll regression test I added. If this code cannot be fixed, it should be removed for good, but I'll leave it to Nate to decide its fate. llvm-svn: 23670
* When preselecting, favor things that have low depth to select first. ThisChris Lattner2005-10-071-5/+8
| | | | | | | | is faster and uses less stack space. This reduces our stack requirement enough to compile sixtrack, and though it's a hack, should be enough until we switch to iterative isel llvm-svn: 23664
* Pull out Call, reducing stack frame size from 6032 bytes to 5184 bytes.Chris Lattner2005-10-061-106/+111
| | | | llvm-svn: 23650
* Pull out setcc, this reduces stack frame size from 7520 to 6032 bytesChris Lattner2005-10-061-115/+117
| | | | llvm-svn: 23649
* Pull two more methods out, reducing stack frame size from 8224 -> 7520 bytesChris Lattner2005-10-061-58/+65
| | | | llvm-svn: 23648
* Add a recursive-iterative hybrid stage to attempt to reduce stack space, thisChris Lattner2005-10-061-45/+94
| | | | | | | | | | | helps but not enough. Start pulling cases out of PPC32DAGToDAGISel::Select. With GCC 4, this function required 8512 bytes of stack space for each invocation (GCC 3 required less than 700 bytes). Pulling this first function out gets us down to 8224. More to come :( llvm-svn: 23647
* another solution to the fsel issue. Instead of having 4 variants, just forceChris Lattner2005-10-021-12/+8
| | | | | | | the comparison to be 64-bits. This is fine because extensions from float to double are free. llvm-svn: 23589
* fsel can take a different FP type for the comparison and for the result. As ↵Chris Lattner2005-10-021-11/+14
| | | | | | | | such split the FSEL family into 4 things instead of just two. llvm-svn: 23588
* Minor tweak to the branch selector. When emitting a two-way branch, and ifChris Lattner2005-10-011-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | we're in a single-mbb loop, make sure to emit the backwards branch as the conditional branch instead of the uncond branch. For example, emit this: LBBl29_z__44: stw r9, 0(r15) stw r9, 4(r15) stw r9, 8(r15) stw r9, 12(r15) addi r15, r15, 16 addi r8, r8, 1 cmpw cr0, r8, r28 ble cr0, LBBl29_z__44 b LBBl29_z__48 *** NOT PART OF LOOP Instead of: LBBl29_z__44: stw r9, 0(r15) stw r9, 4(r15) stw r9, 8(r15) stw r9, 12(r15) addi r15, r15, 16 addi r8, r8, 1 cmpw cr0, r8, r28 bgt cr0, LBBl29_z__48 *** PART OF LOOP! b LBBl29_z__44 The former sequence has one fewer dispatch group for the loop body. llvm-svn: 23582
* fix typoChris Lattner2005-10-011-1/+1
| | | | llvm-svn: 23578
* Modify the ppc backend to use two register classes for FP: F8RC and F4RC.Chris Lattner2005-10-011-17/+56
| | | | | | | These are used to represent float and double values, and the two regclasses contain the same physical registers. llvm-svn: 23577
* Should be using flag and not chain.Jim Laskey2005-09-301-1/+1
| | | | llvm-svn: 23572
* Remove code for patterns that are autogeneratedChris Lattner2005-09-291-30/+9
| | | | llvm-svn: 23532
* Never rely on ReplaceAllUsesWith when selecting, use CodeGenMap instead.Chris Lattner2005-09-291-34/+29
| | | | | | | ReplaceAllUsesWith does not replace scalars SDOperand floating around on the stack, permitting things to be selected multiple times. llvm-svn: 23515
* Autogen MUL, move FP cases togetherChris Lattner2005-09-281-24/+12
| | | | llvm-svn: 23512
* disentangle FP from INT versions of div/mulChris Lattner2005-09-281-18/+16
| | | | llvm-svn: 23511
* Use the autogenerated matcher for ADD/SUBChris Lattner2005-09-281-30/+0
| | | | llvm-svn: 23510
* Add FP versions of the binary operators, keeping the int and fp worlds seperate.Chris Lattner2005-09-281-37/+37
| | | | llvm-svn: 23506
* All (xor *) cases are autogenerated nowChris Lattner2005-09-281-43/+0
| | | | llvm-svn: 23497
* Implement PowerPC/eqv-andc-orc-nor.ll:EQV3Chris Lattner2005-09-281-1/+5
| | | | llvm-svn: 23494
* These nodes are all autogeneratedChris Lattner2005-09-281-44/+0
| | | | llvm-svn: 23489
* Make sure to clear the CodeGenMap after each basic block is selected to avoidChris Lattner2005-09-271-0/+1
| | | | | | cross MBB pollution. llvm-svn: 23470
* we don't need this proto any longerChris Lattner2005-09-131-1/+0
| | | | llvm-svn: 23342
* move the #include for the generated code into the isel class body so weChris Lattner2005-09-131-1/+3
| | | | | | can use/define class methods llvm-svn: 23339
* PowerPC cannot truncstore i1 nativelyChris Lattner2005-09-101-1/+0
| | | | llvm-svn: 23304
* Remove some cases handled by the generated portion of the iselChris Lattner2005-09-071-13/+3
| | | | llvm-svn: 23262
* Implement i64<->fp using the fctidz/fcfid instructions on PowerPC when weNate Begeman2005-09-061-2/+11
| | | | | | | | | are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts, such as the PowerPC 970. This speeds up 189.lucas from 81.99 to 32.64 seconds. llvm-svn: 23250
* include the dag isel fragmentChris Lattner2005-09-031-0/+2
| | | | llvm-svn: 23239
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