Convert these cases to patterns

llvm-svn: 23811

1 files changed, 0 insertions, 28 deletions

diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 207b2e5042f..7cc92694cb3 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -1211,34 +1211,6 @@ SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
       
     // Other cases are autogenerated.
     break;
-  case ISD::TRUNCATE: {
-    assert(N->getValueType(0) == MVT::i32 && 
-           N->getOperand(0).getValueType() == MVT::i64 &&
-           "TRUNCATE only supported for i64 -> i32");
-    SDOperand Op0 = Select(N->getOperand(0));
-    CurDAG->SelectNodeTo(N, PPC::OR8To4, MVT::i32, Op0, Op0);
-    break;
-  }
-  case ISD::ANY_EXTEND:
-    switch(N->getValueType(0)) {
-    default: assert(0 && "Unhandled type in ANY_EXTEND");
-    case MVT::i64: {
-      SDOperand Op0 = Select(N->getOperand(0));
-      CurDAG->SelectNodeTo(N, PPC::OR4To8, MVT::i64, Op0, Op0);
-      break;
-    }
-    }
-    return SDOperand(N, 0);
-  case ISD::ZERO_EXTEND: {
-    assert(N->getValueType(0) == MVT::i64 && 
-           N->getOperand(0).getValueType() == MVT::i32 &&
-           "ZERO_EXTEND only supported for i32 -> i64");
-    SDOperand Op0 = Select(N->getOperand(0));
-    Op0 = CurDAG->getTargetNode(PPC::OR4To8, MVT::i64, Op0, Op0);
-    CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Op0, getI32Imm(0),
-                         getI32Imm(32));
-    return SDOperand(N, 0);
-  }
   case ISD::SHL: {
     unsigned Imm, SH, MB, ME;
     if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&