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| author | Nate Begeman <natebegeman@mac.com> | 2005-10-18 23:23:37 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2005-10-18 23:23:37 +0000 |
| commit | 78afac2ddd5fdff66e53b0cea6dccc978740b874 (patch) | |
| tree | 8a3c7b5cb67ddc0b6beae8555d85f20b97c50c2a /llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | |
| parent | 0a71a9ac86e9a8fb89f1638e600e6b1ae45d0013 (diff) | |
| download | bcm5719-llvm-78afac2ddd5fdff66e53b0cea6dccc978740b874.tar.gz bcm5719-llvm-78afac2ddd5fdff66e53b0cea6dccc978740b874.zip | |
Add the ability to lower return instructions to TargetLowering. This
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).
llvm-svn: 23802
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index c55bd30a2dd..75480930311 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -1206,6 +1206,22 @@ SDOperand PPCDAGToDAGISel::Select(SDOperand Op) { // Other cases are autogenerated. break; + case ISD::ANY_EXTEND: + switch(N->getValueType(0)) { + default: assert(0 && "Unhandled type in ANY_EXTEND"); + case MVT::i64: + CurDAG->SelectNodeTo(N, PPC::OR8, MVT::i64, Select(N->getOperand(0)), + Select(N->getOperand(0))); + break; + } + return SDOperand(N, 0); + case ISD::ZERO_EXTEND: + assert(N->getValueType(0) == MVT::i64 && + N->getOperand(0).getValueType() == MVT::i32 && + "ZERO_EXTEND only supported for i32 -> i64"); + CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Select(N->getOperand(0)), + getI32Imm(32)); + return SDOperand(N, 0); case ISD::SHL: { unsigned Imm, SH, MB, ME; if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && @@ -1393,11 +1409,6 @@ SDOperand PPCDAGToDAGISel::Select(SDOperand Op) { SDOperand Val = Select(N->getOperand(1)); if (N->getOperand(1).getValueType() == MVT::i32) { Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val); - } else if (N->getOperand(1).getValueType() == MVT::i64) { - SDOperand Srl = CurDAG->getTargetNode(PPC::RLDICL, MVT::i64, Val, - getI32Imm(32), getI32Imm(32)); - Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Val); - Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Srl); } else { assert(MVT::isFloatingPoint(N->getOperand(1).getValueType())); Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val); |

