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* Fix Regression/CodeGen/PowerPC/2005-01-14-UndefLong.llChris Lattner2005-01-141-0/+2
| | | | llvm-svn: 19557
* Fix: Regression/CodeGen/PowerPC/2005-01-14-SetSelectCrash.llChris Lattner2005-01-141-1/+2
| | | | llvm-svn: 19555
* This hunk:Chris Lattner2005-01-021-2/+2
| | | | | | | | | | | - unsigned TrueValue = getReg(TrueVal, BB, BB->begin()); + unsigned TrueValue = getReg(TrueVal); Fixes the PPC regressions from last night. The other hunk is just a clarity improvement. llvm-svn: 19263
* Fix a FIXME: Select instructions on longs were miscompiled.Chris Lattner2005-01-011-19/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While we're at it, improve codegen of select instructions. For this testcase: int %test(bool %C, int %A, int %B) { %D = select bool %C, int %A, int %B ret int %D } We used to generate this code: _test: cmpwi cr0, r3, 0 bne .LBB_test_2 ; .LBB_test_1: ; b .LBB_test_3 ; .LBB_test_2: ; or r5, r4, r4 .LBB_test_3: ; or r3, r5, r5 blr Now we emit: _test: cmpwi cr0, r3, 0 bne .LBB_test_2 ; .LBB_test_1: ; or r4, r5, r5 .LBB_test_2: ; or r3, r4, r4 blr -Chris llvm-svn: 19214
* Fix several bugs in 'op x, imm' handling. Foremost is that we now emitChris Lattner2004-11-301-14/+10
| | | | | | | | | | | | | | addi r3, r3, -1 instead of addi r3, r3, 1 for 'sub int X, 1'. Secondarily, this fixes several cases where we could crash given an unsigned constant. And fixes a couple of minor missed optimization cases, such as xor X, ~0U -> not X llvm-svn: 18379
* Fix CodeGen/PowerPC/2004-11-30-shr-var-crash.llChris Lattner2004-11-301-1/+1
| | | | llvm-svn: 18376
* Fix test/Regression/CodeGen/PowerPC/2004-11-29-ShrCrash.llChris Lattner2004-11-301-1/+3
| | | | llvm-svn: 18374
* Fix test/Regression/CodeGen/PowerPC/2004-11-30-shift-crash.llChris Lattner2004-11-301-1/+6
| | | | llvm-svn: 18371
* Remove the ISel->AsmPrinter link via the TargetMachine that was put inNate Begeman2004-11-271-15/+0
| | | | | | | | place to help bring up the PowerPC back end on Darwin. This code is no longer serves any purpose now that the AsmPrinter does the right thing all the time printing GlobalValues. --Cruft. llvm-svn: 18267
* Enable optimization suggested by Chris Lattner to not emit reloc stubs forNate Begeman2004-11-251-1/+1
| | | | | | | | | | | | | | | | | | | static global variables whose addresses are taken. This allows us to convert the following code for taking the address of a static function foo addis r2, r30, ha16(Ll1__2E_foo_2$non_lazy_ptr-"L00001$pb") lwz r3, lo16(Ll1__2E_foo_2$non_lazy_ptr-"L00001$pb")(r2) which also includes linker stub code emitted at the end of the .s file not shown here, and replace it with this: addis r2, r30, ha16(l1__2E_foo_2-"L00001$pb") la r3, lo16(l1__2E_foo_2-"L00001$pb")(r2) which in addition to not needing linker help, also has no load instruction. For those not up on PowerPC mnemonics, la is shorthand for add immediate. llvm-svn: 18239
* Add the same optimization that we do loading from fixed alloca slots toNate Begeman2004-11-241-0/+12
| | | | | | storing to fixed alloca slots. llvm-svn: 18221
* Simplify code a bitChris Lattner2004-11-231-1/+1
| | | | llvm-svn: 18146
* LA is really addi. Be consistent with operand ordering to avoid confusing ↵Chris Lattner2004-11-231-4/+6
| | | | | | the code emitter llvm-svn: 18138
* Fix Shootout-C++/wc, which was broken by my recent changes to emit fewerNate Begeman2004-11-211-5/+6
| | | | | | | | | reg-reg copies. The necessary conditions for this bug are a GEP that is used outside the basic block in which it is defined, whose components other than the pointer are all constant zero, and where the use is selected before the definition (backwards branch to successsor block). llvm-svn: 18084
* Eliminate another 6k register copies that the register allocator would justNate Begeman2004-11-191-8/+14
| | | | | | coalesce out of hbd. Speeds up compilation by 2% (0.6s) llvm-svn: 17987
* Generate fewer reg-reg copies for the register allocator to deal with.Nate Begeman2004-11-191-64/+39
| | | | | | This eliminates over 2000 in hbd alone. llvm-svn: 17973
* Eliminate another common source of moves that the register allocatorNate Begeman2004-11-181-5/+4
| | | | | | | shouldn't be forced to coalesce for us: folded GEP operations. This too fires thousands of times across the testsuite. llvm-svn: 17947
* When accessing the base register for global variables, use the registerNate Begeman2004-11-181-19/+13
| | | | | | | directly rather than making a copy for the register allocator to coalesce. This kills thousands of live intervals across the testsuite. llvm-svn: 17946
* Clean up and fix cast codegen by removing cases that are handled elsewhere,Nate Begeman2004-11-181-19/+8
| | | | | | | and properly emitting signed short to unsigned int. This fixes the last regression vs. the CBE, MultiSource/Applications/hbd. llvm-svn: 17942
* Put int the getReg cast optimization from x86 so that we generate fewerNate Begeman2004-11-081-0/+8
| | | | | | move instructions for the register allocator to coalesce. llvm-svn: 17608
* Disable bogus cast elimination when the cast is used by a setcc instruction.Nate Begeman2004-11-071-4/+4
| | | | llvm-svn: 17583
* Thanks to sabre for pointing out that we were incorrectly codegen'ingNate Begeman2004-11-041-1/+4
| | | | | | | | | int test(int x) { return 32768 - x; } Fixed by teaching the function that checks a constant's validity to be used as an immediate argument about subtract-from instructions. llvm-svn: 17476
* Fix treecc. Also fix a latent bug in emitBinaryConstOperation that wouldNate Begeman2004-10-261-64/+46
| | | | | | allow and const, 0 to be incorrectly codegen'd into a rlwinm instruction. llvm-svn: 17234
* Implement more complete and correct codegen for bitfield inserts, as testedNate Begeman2004-10-241-89/+236
| | | | | | | by the recently committed rlwimi.ll test file. Also commit initial code for bitfield extract, although it is turned off until fully debugged. llvm-svn: 17207
* Kill casts from integer types to unsigned byte, when the cast was only usedNate Begeman2004-10-231-0/+13
| | | | | | | | as the shift amount operand to a shift instruction. This was causing us to emit unnecessary clear operations for code such as: int foo(int x) { return 1 << x; } llvm-svn: 17175
* Adjust to changes in Makefile.rulesReid Spencer2004-10-221-1/+1
| | | | llvm-svn: 17167
* Don't clear or sign extend bool->int. This fires a few dozen times on the ↵Nate Begeman2004-10-201-0/+17
| | | | | | test suite llvm-svn: 17147
* Implement bitfield insert by recognizing the following pattern:Nate Begeman2004-10-171-5/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. optional shift left 2. and x, immX 3. and y, immY 4. or z, x, y ==> rlwimi z, x, y, shift, mask begin, mask end where immX == ~immY and immX is a run of set bits. This transformation fires 32 times on voronoi, once on espresso, and probably several dozen times on external benchmarks such as gcc. To put this in terms of actual code generated for struct B { unsigned a : 3; unsigned b : 2; }; void storeA (struct B *b, int v) { b->a = v;} void storeB (struct B *b, int v) { b->b = v;} Old: _storeA: rlwinm r2, r4, 0, 29, 31 lwz r4, 0(r3) rlwinm r4, r4, 0, 0, 28 or r2, r4, r2 stw r2, 0(r3) blr _storeB: rlwinm r2, r4, 3, 0, 28 rlwinm r2, r2, 0, 27, 28 lwz r4, 0(r3) rlwinm r4, r4, 0, 29, 26 or r2, r2, r4 stw r2, 0(r3) blr New: _storeA: lwz r2, 0(r3) rlwimi r2, r4, 0, 29, 31 stw r2, 0(r3) blr _storeB: lwz r2, 0(r3) rlwimi r2, r4, 3, 27, 28 stw r2, 0(r3) blr llvm-svn: 17078
* Finally fix one of the oldest FIXMEs in the PowerPC backend: correctlyNate Begeman2004-10-161-10/+8
| | | | | | | | | | flag rotate left word immediate then mask insert (rlwimi) as a two-address instruction, and update the ISel usage of the instruction accordingly. This will allow us to properly schedule rlwimi, and use it to efficiently codegen bitfield operations. llvm-svn: 17068
* ADd support for undef and unreachableChris Lattner2004-10-161-4/+8
| | | | llvm-svn: 17050
* Better codegen of binary integer ops with 32 bit immediate operands.Nate Begeman2004-10-151-2/+22
| | | | | | | | | | | | | | | | | | | | This transformation fires a few dozen times across the testsuite. For example, int test2(int X) { return X ^ 0x0FF00FF0; } Old: _test2: lis r2, 4080 ori r2, r2, 4080 xor r3, r3, r2 blr New: _test2: xoris r3, r3, 4080 xori r3, r3, 4080 blr llvm-svn: 17004
* Implement logical and with an immediate that consists of a contiguous blockNate Begeman2004-10-081-5/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of one or more 1 bits (may wrap from least significant bit to most significant bit) as the rlwinm rather than andi., andis., or some longer instructons sequence. int andn4(int z) { return z & -4; } int clearhi(int z) { return z & 0x0000FFFF; } int clearlo(int z) { return z & 0xFFFF0000; } int clearmid(int z) { return z & 0x00FFFF00; } int clearwrap(int z) { return z & 0xFF0000FF; } _andn4: rlwinm r3, r3, 0, 0, 29 blr _clearhi: rlwinm r3, r3, 0, 16, 31 blr _clearlo: rlwinm r3, r3, 0, 0, 15 blr _clearmid: rlwinm r3, r3, 0, 8, 23 blr _clearwrap: rlwinm r3, r3, 0, 24, 7 blr llvm-svn: 16832
* Several fixes and enhancements to the PPC32 backend.Nate Begeman2004-10-071-143/+127
| | | | | | | | | | | | | | | | | | | | | | 1. Fix an illegal argument to getClassB when deciding whether or not to sign extend a byte load. 2. Initial addition of isLoad and isStore flags to the instruction .td file for eventual use in a scheduler. 3. Rewrite of how constants are handled in emitSimpleBinaryOperation so that we can emit the PowerPC shifted immediate instructions far more often. This allows us to emit the following code: int foo(int x) { return x | 0x00F0000; } _foo: .LBB_foo_0: ; entry ; IMPLICIT_DEF oris r3, r3, 15 blr llvm-svn: 16826
* Correct some typeosChris Lattner2004-10-061-3/+3
| | | | llvm-svn: 16770
* Turning on fsel code gen now that we can do so would be good.Nate Begeman2004-10-061-11/+10
| | | | llvm-svn: 16765
* Implement floating point select for lt, gt, le, ge using the powerpc fselNate Begeman2004-10-061-25/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instruction. Now, rather than emitting the following loop out of bisect: .LBB_main_19: ; no_exit.0.i rlwinm r3, r2, 3, 0, 28 lfdx f1, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f2, f2, f1 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3) fcmpu cr0, f1, f4 bge .LBB_main_64 ; no_exit.0.i .LBB_main_63: ; no_exit.0.i b .LBB_main_65 ; no_exit.0.i .LBB_main_64: ; no_exit.0.i fmr f2, f1 .LBB_main_65: ; no_exit.0.i addi r3, r2, 1 rlwinm r3, r3, 3, 0, 28 lfdx f1, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f4, f4, f1 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f5, lo16(.CPI_main_1-"L00000$pb")(r3) fcmpu cr0, f1, f5 bge .LBB_main_67 ; no_exit.0.i .LBB_main_66: ; no_exit.0.i b .LBB_main_68 ; no_exit.0.i .LBB_main_67: ; no_exit.0.i fmr f4, f1 .LBB_main_68: ; no_exit.0.i fadd f1, f2, f4 addis r3, r30, ha16(.CPI_main_2-"L00000$pb") lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3) fmul f1, f1, f2 rlwinm r3, r2, 3, 0, 28 lfdx f2, r3, r28 fadd f4, f2, f1 fcmpu cr0, f4, f0 bgt .LBB_main_70 ; no_exit.0.i .LBB_main_69: ; no_exit.0.i b .LBB_main_71 ; no_exit.0.i .LBB_main_70: ; no_exit.0.i fmr f0, f4 .LBB_main_71: ; no_exit.0.i fsub f1, f2, f1 addi r2, r2, -1 fcmpu cr0, f1, f3 blt .LBB_main_73 ; no_exit.0.i .LBB_main_72: ; no_exit.0.i b .LBB_main_74 ; no_exit.0.i .LBB_main_73: ; no_exit.0.i fmr f3, f1 .LBB_main_74: ; no_exit.0.i cmpwi cr0, r2, -1 fmr f16, f0 fmr f17, f3 bgt .LBB_main_19 ; no_exit.0.i We emit this instead: .LBB_main_19: ; no_exit.0.i rlwinm r3, r2, 3, 0, 28 lfdx f1, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f2, f2, f1 fsel f1, f1, f1, f2 addi r3, r2, 1 rlwinm r3, r3, 3, 0, 28 lfdx f2, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f4, f4, f2 fsel f2, f2, f2, f4 fadd f1, f1, f2 addis r3, r30, ha16(.CPI_main_2-"L00000$pb") lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3) fmul f1, f1, f2 rlwinm r3, r2, 3, 0, 28 lfdx f2, r3, r28 fadd f4, f2, f1 fsub f5, f0, f4 fsel f0, f5, f0, f4 fsub f1, f2, f1 addi r2, r2, -1 fsub f2, f1, f3 fsel f3, f2, f3, f1 cmpwi cr0, r2, -1 fmr f16, f0 fmr f17, f3 bgt .LBB_main_19 ; no_exit.0.i llvm-svn: 16764
* Generate better code by being far less clever when it comes to the select ↵Nate Begeman2004-09-291-7/+17
| | | | | | instruction. Don't create overlapping register lifetimes llvm-svn: 16580
* improve Type::BoolTy codegen by eliminating unnecessary clears and sign extendsNate Begeman2004-09-291-1/+8
| | | | llvm-svn: 16578
* To go along with sabre's improved InstCombining, improve recognition ofNate Begeman2004-09-291-21/+9
| | | | | | | | | | | | | | | integers that we can use as immediate values in instructions. Example from yacr2: - lis r10, -1 - ori r10, r10, 65535 - add r28, r28, r10 + addi r28, r28, -1 addi r7, r7, 1 addi r9, r9, 1 b .LBB_main_9 ; loopentry.1.i214 llvm-svn: 16566
* Correct some BuildMI arguments for the upcoming simple schedulerNate Begeman2004-09-271-1/+1
| | | | llvm-svn: 16519
* Fix the last of the major PPC GEP folding deficiencies. This will allowNate Begeman2004-09-231-178/+163
| | | | | | | | the ISel to use indexed and non-zero immediate offsets for GEPs that have more than one use. This is common for instruction sequences such as a load followed by a modify and store to the same address. llvm-svn: 16493
* add optimized code sequences for setcc x, 0Nate Begeman2004-09-221-5/+92
| | | | llvm-svn: 16478
* s/ISel/PPC32ISel/ to have unique class names for debugging via gdb because theMisha Brukman2004-09-211-87/+90
| | | | | | C++ front-end in gcc does not mangle classes in anonymous namespaces correctly. llvm-svn: 16470
* All PPC instructions are now auto-printedNate Begeman2004-09-041-3/+4
| | | | | | | 32 and 64 bit AsmWriters unified Darwin and AIX specific features of AsmWriter split out llvm-svn: 16163
* Convert remaining X-Form and Pseudo instructions over to asm writerNate Begeman2004-09-021-2/+2
| | | | llvm-svn: 16142
* Changes For Bug 352Reid Spencer2004-09-011-2/+2
| | | | | | | | Move include/Config and include/Support into include/llvm/Config, include/llvm/ADT and include/llvm/Support. From here on out, all LLVM public header files must be under include/llvm/. llvm-svn: 16137
* Implement the following missing functionality in the PPC backend:Nate Begeman2004-08-291-44/+135
| | | | | | | | | cast fp->bool cast ulong->fp algebraic right shift long by non-constant value These changes tested across most of the test suite. Fixes Regression/casts llvm-svn: 16081
* Kill a majority of unnecessary sign extensions for byte loadsNate Begeman2004-08-221-12/+30
| | | | llvm-svn: 15991
* Back out branchless SetCC code. While it helped a lot in some cases, itNate Begeman2004-08-211-188/+25
| | | | | | | | hurt a lot in others. Instead, improve branching version of SetCC and Select instructions. The old code will be in CVS should we ever need to dig it up again. llvm-svn: 15979
* Implement code to convert SetCC into straight line code where appropriate. ↵Nate Begeman2004-08-201-22/+169
| | | | | | Add necessary instructions for this transformation to the .td file. llvm-svn: 15952
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