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| author | Nate Begeman <natebegeman@mac.com> | 2004-11-21 05:14:06 +0000 | 
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2004-11-21 05:14:06 +0000 | 
| commit | 6c9375b20c1176eee6da720c9de6f5bc8143cbdc (patch) | |
| tree | 36739399464aa9374bdb4f17b1f78452443f2e47 /llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp | |
| parent | f530831f842047ccdabe4eddb11b23c9dcb9afd2 (diff) | |
| download | bcm5719-llvm-6c9375b20c1176eee6da720c9de6f5bc8143cbdc.tar.gz bcm5719-llvm-6c9375b20c1176eee6da720c9de6f5bc8143cbdc.zip | |
Fix Shootout-C++/wc, which was broken by my recent changes to emit fewer
reg-reg copies.  The necessary conditions for this bug are a GEP that is
used outside the basic block in which it is defined, whose components
other than the pointer are all constant zero, and where the use is
selected before the definition (backwards branch to successsor block).
llvm-svn: 18084
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp | 11 | 
1 files changed, 6 insertions, 5 deletions
| diff --git a/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp b/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp index c4babe06147..83ace163939 100644 --- a/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp +++ b/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp @@ -3835,18 +3835,19 @@ void PPC32ISel::emitGEPOperation(MachineBasicBlock *MBB,    unsigned TargetReg = getReg(GEPI, MBB, IP);    unsigned basePtrReg = getReg(Src, MBB, IP); -  if ((indexReg == 0) && remainder->isNullValue()) -    RegMap[GEPI] = basePtrReg; - +  if ((indexReg == 0) && remainder->isNullValue()) { +    BuildMI(*MBB, IP, PPC::OR, 2, TargetReg).addReg(basePtrReg) +      .addReg(basePtrReg); +    return; +  }    if (!remainder->isNullValue()) {      unsigned TmpReg = (indexReg == 0) ? TargetReg : makeAnotherReg(Type::IntTy);      emitBinaryConstOperation(MBB, IP, basePtrReg, remainder, 0, TmpReg);      basePtrReg = TmpReg;    } -  if (indexReg != 0) {  +  if (indexReg != 0)      BuildMI(*MBB, IP, PPC::ADD, 2, TargetReg).addReg(indexReg)        .addReg(basePtrReg); -  }  }  /// visitAllocaInst - If this is a fixed size alloca, allocate space from the | 

