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path: root/llvm/lib/Target/PTX/PTXSubtarget.cpp
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* Remove the PTX back-end and all of its artifacts (triple, etc.)Justin Holewinski2012-05-241-68/+0
| | | | | | | | This back-end was deprecated in favor of the NVPTX back-end. NV_CONTRIB llvm-svn: 157417
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Fix some leftover control reaches end of non-void function warnings.Benjamin Kramer2012-01-101-0/+1
| | | | llvm-svn: 147874
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-101-1/+0
| | | | llvm-svn: 147855
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+2
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-17/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-1/+1
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng2011-07-091-0/+17
| | | | | | | | | CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. llvm-svn: 134795
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-081-1/+2
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-071-2/+2
| | | | llvm-svn: 134606
* Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng2011-07-011-3/+1
| | | | llvm-svn: 134281
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-011-1/+1
| | | | llvm-svn: 134259
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-011-1/+7
| | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-301-3/+5
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* PTX: Re-work target sm/compute selection and add some basic GPUJustin Holewinski2011-06-241-4/+14
| | | | | | targets: g80, gt200, gf100(fermi) llvm-svn: 133799
* PTX: add flag to disable mad/fma selectionJustin Holewinski2011-05-181-1/+2
| | | | | | Patch by Dan Bailey llvm-svn: 131537
* PTX: add PTX 2.3 language targetJustin Holewinski2011-05-061-0/+1
| | | | | | Patch by Wei-Ren Chen llvm-svn: 130980
* PTX: Add intrinsics to list of built-in intrinsics, which allows them to beJustin Holewinski2011-04-201-2/+3
| | | | | | | | | | used by Clang. To help Clang integration, the PTX target has been split into two targets: ptx32 and ptx64, depending on the desired pointer size. - Add GCCBuiltin class to all intrinsics - Split PTX target into ptx32 and ptx64 llvm-svn: 129851
* PTX: Set PTX 2.0 as the minimum supported versionJustin Holewinski2011-03-151-2/+2
| | | | | | | | - Remove PTX 1.4 code generation - Change type of intrinsics to .v4.i32 instead of .v4.i16 - Add and/or/xor integer instructions llvm-svn: 127677
* Add 64-bit addressing to PTX backendChe-Liang Chiou2011-03-021-1/+3
| | | | | | | | | | - Add '64bit' sub-target option. - Select 32-bit/64-bit loads/stores based on '64bit' option. - Fix function parameter order. Patch by Justin Holewinski llvm-svn: 126837
* Extend initial support for primitive types in PTX backendChe-Liang Chiou2011-03-021-3/+24
| | | | | | | | | | | | | | - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824
* Add the exit instruction to the PTX target.Eric Christopher2010-09-181-0/+23
Patch by Che-Liang Chiou <clchiou@gmail.com>! llvm-svn: 114294
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