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* [mips] Mark P5600 scheduling model as completeSimon Atanasyan2019-07-021-1/+1
| | | | llvm-svn: 364902
* [mips] Add missing schedinfo for FPU load/store/conv instructionsSimon Atanasyan2019-07-021-4/+10
| | | | llvm-svn: 364900
* [mips] Map SNOP, NOP to the P5600Nop scheduler resourceSimon Atanasyan2019-07-021-2/+8
| | | | llvm-svn: 364899
* [mips] Add missing schedinfo for MIPSeh_return[32|64] instructionsSimon Atanasyan2019-07-011-1/+1
| | | | llvm-svn: 364850
* [mips] Add virtualization ASE to P5600 scheduling definitionsSimon Atanasyan2019-07-011-0/+5
| | | | llvm-svn: 364849
* [mips] Add missing schedinfo for LONG_BRANCH_* instructionsSimon Atanasyan2019-07-012-11/+27
| | | | llvm-svn: 364848
* [mips] Add missing schedinfo for MSA and ASE instructionsSimon Atanasyan2019-07-013-2/+12
| | | | llvm-svn: 364757
* [mips] Add missing schedinfo for atomic instructionsSimon Atanasyan2019-07-012-3/+22
| | | | llvm-svn: 364756
* [mips] Add missing schedinfo for ADJCALLSTACKDOWN, ADJCALLSTACKUPSimon Atanasyan2019-07-011-1/+1
| | | | llvm-svn: 364755
* [mips] Mark pseudo select instructions by the `hasNoSchedulingInfo` tagSimon Atanasyan2019-06-271-2/+2
| | | | llvm-svn: 364540
* [mips] Add new items to the list of features unsupported by P5600Simon Atanasyan2019-06-271-3/+3
| | | | llvm-svn: 364539
* [mips] Add GPR_64 predicate to some mov[zn] instructionsSimon Atanasyan2019-06-271-8/+10
| | | | llvm-svn: 364527
* [mips] Fix indentation and split long lines. NFCSimon Atanasyan2019-06-271-5/+5
| | | | llvm-svn: 364526
* [mips] Reformat MSA instruction definitions. NFCSimon Atanasyan2019-06-271-46/+32
| | | | llvm-svn: 364525
* [GlobalISel] Accept multiple vregs for lowerCall's resultDiana Picus2019-06-271-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Change the interface of CallLowering::lowerCall to accept several virtual registers for the call result, instead of just one. This is a follow-up to D46018. CallLowering::lowerReturn was similarly refactored in D49660 and lowerFormalArguments in D63549. With this change, we no longer pack the virtual registers generated for aggregates into one big lump before delegating to the target. Therefore, the target can decide itself whether it wants to handle them as separate pieces or use one big register. ARM and AArch64 have been updated to use the passed in virtual registers directly, which means we no longer need to generate so many merge/extract instructions. NFCI for AMDGPU, Mips and X86. Differential Revision: https://reviews.llvm.org/D63550 llvm-svn: 364511
* [GlobalISel] Accept multiple vregs in lowerFormalArgsDiana Picus2019-06-272-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the interface of CallLowering::lowerFormalArguments to accept several virtual registers for each formal argument, instead of just one. This is a follow-up to D46018. CallLowering::lowerReturn was similarly refactored in D49660. lowerCall will be refactored in the same way in follow-up patches. With this change, we forward the virtual registers generated for aggregates to CallLowering. Therefore, the target can decide itself whether it wants to handle them as separate pieces or use one big register. We also copy the pack/unpackRegs helpers to CallLowering to facilitate this. ARM and AArch64 have been updated to use the passed in virtual registers directly, which means we no longer need to generate so many merge/extract instructions. AArch64 seems to have had a bug when lowering e.g. [1 x i8*], which was put into a s64 instead of a p0. Added a test-case which illustrates the problem more clearly (it crashes without this patch) and fixed the existing test-case to expect p0. AMDGPU has been updated to unpack into the virtual registers for kernels. I think the other code paths fall back for aggregates, so this should be NFC. Mips doesn't support aggregates yet, so it's also NFC. x86 seems to have code for dealing with aggregates, but I couldn't find the tests for it, so I just added a fallback to DAGISel if we get more than one virtual register for an argument. Differential Revision: https://reviews.llvm.org/D63549 llvm-svn: 364510
* [GlobalISel] Allow multiple VRegs in ArgInfo. NFCDiana Picus2019-06-271-5/+9
| | | | | | | | | | | Allow CallLowering::ArgInfo to contain more than one virtual register. This is useful when passes split aggregates into several virtual registers, but need to also provide information about the original type to the call lowering. Used in follow-up patches. Differential Revision: https://reviews.llvm.org/D63548 llvm-svn: 364509
* GlobalISel: Remove unsigned variant of SrcOpMatt Arsenault2019-06-245-40/+41
| | | | | | | | | Force using Register. One downside is the generated register enums require explicit conversion. llvm-svn: 364194
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-245-52/+52
| | | | | | | | | Avoids using a plain unsigned for registers throughoug codegen. Doesn't attempt to change every register use, just something a little more than the set needed to build after changing the return type of MachineOperand::getReg(). llvm-svn: 364191
* Simplify std::lower_bound with llvm::{bsearch,lower_bound}. NFCFangrui Song2019-06-212-8/+3
| | | | llvm-svn: 364006
* [MIPS GlobalISel] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off ↵Fangrui Song2019-06-212-2/+4
| | | | | | builds after D63541 llvm-svn: 364003
* [MIPS GlobalISel] Select integer to floating point conversionsPetar Avramovic2019-06-202-0/+21
| | | | | | | | Select G_SITOFP and G_UITOFP for MIPS32. Differential Revision: https://reviews.llvm.org/D63542 llvm-svn: 363912
* [MIPS GlobalISel] Select floating point to integer conversionsPetar Avramovic2019-06-203-0/+50
| | | | | | | | Select G_FPTOSI and G_FPTOUI for MIPS32. Differential Revision: https://reviews.llvm.org/D63541 llvm-svn: 363911
* [mips] Mark the `lwupc` instruction as MIPS64 R6 onlySimon Atanasyan2019-06-192-3/+3
| | | | | | | | | | The "The MIPS64 Instruction Set Reference Manual" [1] states that the `lwupc` is MIPS64 Release 6 only. It should not be supported for 32-bit CPUs. [1] https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf llvm-svn: 363886
* [mips] Add (GPR|PTR)_64 predicates to PseudoReturn64 and ↵Simon Atanasyan2019-06-191-2/+2
| | | | | | | | | PseudoIndirectHazardBranch64 This patch is one of a series of patches. The goal is to make P5600 scheduler model complete and turn on the `CompleteModel` flag. llvm-svn: 363885
* [mips] Add more strict predicates to the RSQRT_S_MM and TAILCALL_MMSimon Atanasyan2019-06-182-2/+3
| | | | | | | This patch is one of a series of patches. The goal is to make P5600 scheduler model complete and turn on the `CompleteModel` flag. llvm-svn: 363703
* [mips] Add PTR_64 and GPR_64 predicates to some MIPS 64-bit instructionsSimon Atanasyan2019-06-182-15/+17
| | | | | | | | | | | | | | | Add `IsGP64bit` and `IsPTR64bit` to the list of `UnsupportedFeatures` of the P5600 scheduling definitions. Also mark some MIPS 64-bit instructions by PTR_64 and GPR_64 predicates. This reduces number of "No schedule information for" and "lacks information for" errors in case of marking this scheduler model as complete. This patch is one of a series of patches. The goal is to make P5600 scheduler model complete and turn on the `CompleteModel` flag. Differential Revision: https://reviews.llvm.org/D63237 llvm-svn: 363702
* [mips] Set the hasNoSchedulingInfo flag for the `MipsAsmPseudoInst`Simon Atanasyan2019-06-181-0/+1
| | | | | | | | | | | | | | Set the hasNoSchedulingInfo flag for the`MipsAsmPseudoInst`. These pseudo-instructions are never used by codegen. This flag allows to reduce number of "No schedule information for" and "lacks information for" errors in case of marking a scheduler model as complete. This patch is one of a series of patches. The goal is to make P5600 scheduler model complete and turn on the `CompleteModel` flag. Differential Revision: https://reviews.llvm.org/D63236 llvm-svn: 363701
* [Mips] Add s.d instruction alias for Mips1Simon Atanasyan2019-06-122-0/+58
| | | | | | | | | | | Add support for s.d instruction for Mips1 which expands into two swc1 instructions. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D63199 llvm-svn: 363184
* [TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests ↵Simon Pilgrim2019-06-124-13/+9
| | | | | | | | | | | | | | (PR42123) As discussed on D62910, we need to check whether particular types of memory access are allowed, not just their alignment/address-space. This NFC patch adds a MachineMemOperand::Flags argument to allowsMemoryAccess and allowsMisalignedMemoryAccesses, and wires up calls to pass the relevant flags to them. If people are happy with this approach I can then update X86TargetLowering::allowsMisalignedMemoryAccesses to handle misaligned NT load/stores. Differential Revision: https://reviews.llvm.org/D63075 llvm-svn: 363179
* Revert CMake: Make most target symbols hidden by defaultTom Stellard2019-06-116-6/+6
| | | | | | | | | | | | | | | This reverts r362990 (git commit 374571301dc8e9bc9fdd1d70f86015de198673bd) This was causing linker warnings on Darwin: ld: warning: direct access in function 'llvm::initializeEvexToVexInstPassPass(llvm::PassRegistry&)' from file '../../lib/libLLVMX86CodeGen.a(X86EvexToVex.cpp.o)' to global weak symbol 'void std::__1::__call_once_proxy<std::__1::tuple<void* (&)(llvm::PassRegistry&), std::__1::reference_wrapper<llvm::PassRegistry>&&> >(void*)' from file '../../lib/libLLVMCore.a(Verifier.cpp.o)' means the weak symbol cannot be overridden at runtime. This was likely caused by different translation units being compiled with different visibility settings. llvm-svn: 363028
* CMake: Make most target symbols hidden by defaultTom Stellard2019-06-106-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For builds with LLVM_BUILD_LLVM_DYLIB=ON and BUILD_SHARED_LIBS=OFF this change makes all symbols in the target specific libraries hidden by default. A new macro called LLVM_EXTERNAL_VISIBILITY has been added to mark symbols in these libraries public, which is mainly needed for the definitions of the LLVMInitialize* functions. This patch reduces the number of public symbols in libLLVM.so by about 25%. This should improve load times for the dynamic library and also make abi checker tools, like abidiff require less memory when analyzing libLLVM.so One side-effect of this change is that for builds with LLVM_BUILD_LLVM_DYLIB=ON and LLVM_LINK_LLVM_DYLIB=ON some unittests that access symbols that are no longer public will need to be statically linked. Before and after public symbol counts (using gcc 8.2.1, ld.bfd 2.31.1): nm before/libLLVM-9svn.so | grep ' [A-Zuvw] ' | wc -l 36221 nm after/libLLVM-9svn.so | grep ' [A-Zuvw] ' | wc -l 26278 Reviewers: chandlerc, beanz, mgorny, rnk, hans Reviewed By: rnk, hans Subscribers: Jim, hiraditya, michaelplatings, chapuni, jholewinski, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, kristina, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D54439 llvm-svn: 362990
* [MIPS GlobalISel] Select sqrtPetar Avramovic2019-06-062-2/+3
| | | | | | | | Select G_FSQRT for MIPS32. Differential Revision: https://reviews.llvm.org/D62905 llvm-svn: 362692
* [MIPS GlobalISel] Select fabsPetar Avramovic2019-06-063-2/+13
| | | | | | | | Select G_FABS for MIPS32. Differential Revision: https://reviews.llvm.org/D62903 llvm-svn: 362690
* [MIPS GlobalISel] Select fpext and fptruncPetar Avramovic2019-06-062-0/+14
| | | | | | | | Select G_FPEXT and G_FPTRUNC for MIPS32. Differential Revision: https://reviews.llvm.org/D62902 llvm-svn: 362689
* [MIPS GlobalISel] Select floor and ceilPetar Avramovic2019-06-061-0/+3
| | | | | | | | Select G_FFLOOR and G_FCEIL for MIPS32. Differential Revision: https://reviews.llvm.org/D62901 llvm-svn: 362688
* [MIPS GlobalISel] Select fcmpPetar Avramovic2019-06-053-0/+94
| | | | | | | | Select floating point compare for MIPS32. Differential Revision: https://reviews.llvm.org/D62721 llvm-svn: 362603
* [mips] Extend range of register indexes accepted by cfcmsa/ctcmsaSimon Atanasyan2019-06-012-13/+9
| | | | | | | | | | | | | | | | | The `cfcmsa` and `ctcmsa` instructions accept index of MSA control register. The MIPS64 SIMD Architecture define eight MSA control registers. But register index for `cfcmsa` and `ctcmsa` instructions might be any number in 0..31 range. If the index is greater then 7, `cfcmsa` writes zero to the destination registers and `ctcmsa` does nothing [1]. [1] MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD Architecture Module https://www.mips.com/?do-download=the-mips64-simd-architecture-module Differential Revision: https://reviews.llvm.org/D62597 llvm-svn: 362299
* [MIPS GlobalISel] Handle position independent code Petar Avramovic2019-05-315-19/+79
| | | | | | | | | | | | | Handle position independent code for MIPS32. When callee is global address, lower call will emit callee as G_GLOBAL_VALUE and add target flag if needed. Support $gp in getRegBankFromRegClass(). Select G_GLOBAL_VALUE, specially handle case when there are target flags attached by lowerCall. Differential Revision: https://reviews.llvm.org/D62589 llvm-svn: 362210
* [mips] Move initGlobalBaseReg to MipsFunctionInfo. NFCPetar Avramovic2019-05-314-94/+93
| | | | | | | | | | | Move initGlobalBaseReg from MipsSEDAGToDAGISel to MipsFunctionInfo. This way functions used for handling position independent code during instruction selection, getGlobalBaseReg and initGlobalBaseReg, end up in same class. Differential Revision: https://reviews.llvm.org/D62586 llvm-svn: 362206
* [MIPS GlobalISel] Lower call for callee that is registerPetar Avramovic2019-05-311-6/+8
| | | | | | | | | Lower call for callee that is register for MIPS32. Register should contain callee function address. Differential Revision: https://reviews.llvm.org/D62585 llvm-svn: 362204
* [mips] Iterate over MSACtrlRegClass to reserve all MSA control registers. NFCSimon Atanasyan2019-05-291-8/+2
| | | | llvm-svn: 361965
* [mips] Use range-based for loops. NFCSimon Atanasyan2019-05-291-8/+4
| | | | llvm-svn: 361964
* [mips] Always check that `shift and add` optimization is efficient.Simon Atanasyan2019-05-241-26/+31
| | | | | | | | | | | | | | The D45316 introduced the `shouldTransformMulToShiftsAddsSubs` function to check that breaking down constant multiplications into a series of shifts, adds, and subs is efficient. Unfortunately, this function does not check maximum number of steps on all paths of the algorithm. This patch fixes this bug. Fix for PR41929. Differential Revision: https://reviews.llvm.org/D62166 llvm-svn: 361606
* [ARM] Support .reloc *, R_ARM_NONE, *Fangrui Song2019-05-173-8/+3
| | | | | | | | | | | | | | | | R_ARM_NONE can be used to create references among sections. When --gc-sections is used, the referenced section will be retained if the origin section is retained. Add a generic MCFixupKind FK_NONE as this kind of no-op relocation is ubiquitous on ELF and COFF, and probably available on many other binary formats. See D62014. Reviewed By: peter.smith Differential Revision: https://reviews.llvm.org/D61992 llvm-svn: 360980
* [mips] Use range-based `for` loops. NFCSimon Atanasyan2019-05-151-20/+17
| | | | llvm-svn: 360817
* [mips] LLVM and GAS now use same instructions for CFA Definition. NFCISimon Atanasyan2019-05-151-1/+1
| | | | | | | | | | | | | LLVM previously used `DW_CFA_def_cfa` instruction in .eh_frame to set the register and offset for current CFA rule. We change it to `DW_CFA_def_cfa_register` which is the same one used by GAS that only changes the register but keeping the old offset. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D61899 llvm-svn: 360765
* [Mips] Create a TargetInfo header. NFCRichard Trieu2019-05-148-16/+29
| | | | | | | | Move the declarations of getThe<Name>Target() functions into a new header in TargetInfo and make users of these functions include this new header. This fixes a layering problem. llvm-svn: 360727
* [Mips] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1113-37/+11
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360497
* [TargetLowering] Change getOptimalMemOpType to take a function attribute listSjoerd Meijer2019-04-302-6/+5
| | | | | | | | | | | | The MachineFunction wasn't used in getOptimalMemOpType, but more importantly, this allows reuse of findOptimalMemOpLowering that is calling getOptimalMemOpType. This is the groundwork for the changes in D59766 and D59787, that allows implementation of TTI::getMemcpyCost. Differential Revision: https://reviews.llvm.org/D59785 llvm-svn: 359537
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