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* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-0216-37/+37
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Resort the #include lines in include/... and lib/... with theChandler Carruth2013-01-021-1/+1
| | | | | | | | | | utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. llvm-svn: 171362
* [mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardwareAkira Hatanaka2012-12-213-54/+73
| | | | | | instructions. llvm-svn: 170956
* [mips] Refactor SYNC and multiply/divide instructions.Akira Hatanaka2012-12-213-54/+59
| | | | llvm-svn: 170955
* [mips] Refactor BAL instructions.Akira Hatanaka2012-12-212-10/+40
| | | | llvm-svn: 170954
* [mips] Fix encoding of BAL instruction. Also, fix assembler test case whichAkira Hatanaka2012-12-211-1/+1
| | | | | | was not catching the error. llvm-svn: 170953
* [mips] Refactor jump, jump register, jump-and-link and nop instructions.Akira Hatanaka2012-12-213-41/+50
| | | | llvm-svn: 170952
* [mips] Refactor load/store left/right and load-link and store-conditionalAkira Hatanaka2012-12-212-79/+52
| | | | | | instructions. llvm-svn: 170950
* [mips] Refactor load/store instructions.Akira Hatanaka2012-12-212-62/+34
| | | | llvm-svn: 170948
* [mips] Remove unnecessary isPseudo parameter.Akira Hatanaka2012-12-211-24/+16
| | | | llvm-svn: 170947
* [mips] Refactor LUI instruction.Akira Hatanaka2012-12-213-6/+17
| | | | llvm-svn: 170944
* [mips] Refactor count leading zero or one instructions.Akira Hatanaka2012-12-213-20/+29
| | | | llvm-svn: 170942
* [mips] Refactor sign-extension-in-register instructions.Akira Hatanaka2012-12-213-11/+21
| | | | llvm-svn: 170940
* [mips] Refactor instructions which copy from and to HI/LO registers.Akira Hatanaka2012-12-213-22/+35
| | | | llvm-svn: 170939
* [mips] Refactor logical NOR instructions.Akira Hatanaka2012-12-212-7/+6
| | | | llvm-svn: 170937
* [mips] Move instruction definitions in MipsInstrInfo.td.Akira Hatanaka2012-12-211-37/+39
| | | | llvm-svn: 170936
* Call llvm_unreachable instead of assert.Reed Kotler2012-12-211-1/+1
| | | | llvm-svn: 170822
* Implement cfi_def_cfa_offset. "Make check" test case for this comming in theReed Kotler2012-12-201-0/+27
| | | | | | | next few days but it's already tested a lot from test-suite and works fine. This patch completes almost 100% pass of test-suite for mips 16. llvm-svn: 170674
* There is one more patch to finish large frames. Make sure we assertReed Kotler2012-12-202-0/+8
| | | | | | on code that has large frames which will not yet compile correctly. llvm-svn: 170673
* set register class properly for mips16 hereReed Kotler2012-12-201-1/+2
| | | | llvm-svn: 170669
* This assert is overly restrictive and does not work for mips16.Reed Kotler2012-12-201-1/+0
| | | | llvm-svn: 170667
* Turn on register scavenger for Mips 16Reed Kotler2012-12-202-0/+39
| | | | | | | We use an unused Mips 32 register for the emergency slot instead of using the stack. llvm-svn: 170665
* [mips] Refactor SLT (set on less than) instructions. Separate encodingAkira Hatanaka2012-12-203-22/+32
| | | | | | information from the rest. llvm-svn: 170664
* [mips] Refactor unconditional branch instruction. Separate encoding informationAkira Hatanaka2012-12-202-6/+15
| | | | | | from the rest. llvm-svn: 170663
* [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass Akira Hatanaka2012-12-206-69/+64
| | | | | | parameter. llvm-svn: 170661
* [mips] Delete definition of CPRESTORE instruction.Akira Hatanaka2012-12-201-8/+0
| | | | llvm-svn: 170660
* [mips] Refactor conditional branch instructions with one register operand.Akira Hatanaka2012-12-203-14/+24
| | | | | | Separate encoding information from the rest. llvm-svn: 170659
* [mips] Refactor conditional branch instructions with two register operands.Akira Hatanaka2012-12-203-8/+22
| | | | | | Separate encoding information from the rest. llvm-svn: 170657
* fix most of remaining issues with large frames.Reed Kotler2012-12-204-18/+195
| | | | | | | | | | these patches are tested a lot by test-suite but make check tests are forthcoming once the next few patches that complete this are committed. with the next few patches the pass rate for mips16 is near 100% llvm-svn: 170656
* [mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copyAkira Hatanaka2012-12-201-5/+5
| | | | | | | | | | | physical register $r1 to $r0. GNU disassembler recognizes an "or" instruction as a "move", and this change makes the disassembled code easier to read. Original patch by Reed Kotler. llvm-svn: 170655
* [mips] Change the order of template parameters. Move the default parameters toAkira Hatanaka2012-12-202-29/+30
| | | | | | the end. llvm-svn: 170651
* [mips] Refactor shift instructions with register operands. Separate encodingAkira Hatanaka2012-12-203-15/+28
| | | | | | information from the rest. llvm-svn: 170650
* [mips] Refactor shift immediate instructions. Separate encoding informationAkira Hatanaka2012-12-203-36/+44
| | | | | | from the rest. llvm-svn: 170649
* [mips] Refactor arithmetic and logic instructions with immediate operands.Akira Hatanaka2012-12-203-22/+39
| | | | | | Separate encoding information from the rest. llvm-svn: 170648
* [mips] Refactor arithmetic and logic instructions. Separate encodingAkira Hatanaka2012-12-203-28/+40
| | | | | | information from the rest. llvm-svn: 170647
* [mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR andAkira Hatanaka2012-12-202-43/+30
| | | | | | ArithLogicI as the instruction base classes. llvm-svn: 170642
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-193-13/+1
| | | | llvm-svn: 170578
* Add some missing Defs and Uses.Reed Kotler2012-12-191-1/+11
| | | | llvm-svn: 170493
* This patch is needed to make c++ exceptions work for mips16.Reed Kotler2012-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mips16 is really a processor decoding mode (ala thumb 1) and in the same program, mips16 and mips32 functions can exist and can call each other. If a jal type instruction encounters an address with the lower bit set, then the processor switches to mips16 mode (if it is not already in it). If the lower bit is not set, then it switches to mips32 mode. The linker knows which functions are mips16 and which are mips32. When relocation is performed on code labels, this lower order bit is set if the code label is a mips16 code label. In general this works just fine, however when creating exception handling tables and dwarf, there are cases where you don't want this lower order bit added in. This has been traditionally distinguished in gas assembly source by using a different syntax for the label. lab1: ; this will cause the lower order bit to be added lab2=. ; this will not cause the lower order bit to be added In some cases, it does not matter because in dwarf and debug tables the difference of two labels is used and in that case the lower order bits subtract each other out. To fix this, I have added to mcstreamer the notion of a debuglabel. The default is for label and debug label to be the same. So calling EmitLabel and EmitDebugLabel produce the same result. For various reasons, there is only one set of labels that needs to be modified for the mips exceptions to work. These are the "$eh_func_beginXXX" labels. Mips overrides the debug label suffix from ":" to "=." . This initial patch fixes exceptions. More changes most likely will be needed to DwarfCFException to make all of this work for actual debugging. These changes will be to emit debug labels in some places where a simple label is emitted now. Some historical discussion on this from gcc can be found at: http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html llvm-svn: 170279
* This code implements most of mips16 hardfloat as it is done by gcc.Reed Kotler2012-12-152-0/+46
| | | | | | | | | | | | | | | | In this case, essentially it is soft float with different library routines. The next step will be to make this fully interoperational with mips32 floating point and that requires creating stubs for functions with signatures that contain floating point types. I have a more sophisticated design for mips16 hardfloat which I hope to implement at a later time that directly does floating point without the need for function calls. The mips16 encoding has no floating point instructions so one needs to switch to mips32 mode to execute floating point instructions. llvm-svn: 170259
* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-131-3/+3
| | | | | | | | | | | | Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. This is the second attempt. In the first attempt (r169837), a few getSimpleVT() were hoisted too far, detected by bootstrap failures. llvm-svn: 170104
* [mips] Do not copy GOT address to register $gp if the function being called hasAkira Hatanaka2012-12-131-4/+9
| | | | | | internal linkage. llvm-svn: 170092
* [mips] Delete all floating point instruction classes that are no longer used.Akira Hatanaka2012-12-133-279/+2
| | | | | | No functionality change. llvm-svn: 170084
* [mips] Modify definitions of floating point conditional move instructions.Akira Hatanaka2012-12-132-24/+110
| | | | | | No functionality change. llvm-svn: 170080
* [mips] Modify definitions of floating point comparison instructions.Akira Hatanaka2012-12-132-9/+30
| | | | | | No functionality change. llvm-svn: 170077
* [mips] Modify definitions of floating point branch instructions.Akira Hatanaka2012-12-132-2/+26
| | | | | | No functionality change. llvm-svn: 170076
* [mips] Modify definitions of floating point indexed load and store instructions.Akira Hatanaka2012-12-132-14/+59
| | | | | | No functionality change. llvm-svn: 170075
* [mips] Modify definitions of floating point multiply-add/sub instructions.Akira Hatanaka2012-12-132-12/+46
| | | | | | No functionality change. llvm-svn: 170073
* [mips] Modify definitions of floating point load and store instructions.Akira Hatanaka2012-12-132-10/+35
| | | | | | No functionality change. llvm-svn: 170072
* [mips] Modify definitions of move from/to coprocessor instructions.Akira Hatanaka2012-12-132-21/+30
| | | | | | No functionality change. llvm-svn: 170071
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