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| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-21 22:46:07 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-21 22:46:07 +0000 |
| commit | e738efc95b18d328ad796225fd8d8785afc61612 (patch) | |
| tree | 49e7601677b8cddb8f13e3700edbec6fefa3c5e7 /llvm/lib/Target/Mips | |
| parent | 895e1cb2aa799d5f4d83fc4b3be9816bb152b7e3 (diff) | |
| download | bcm5719-llvm-e738efc95b18d328ad796225fd8d8785afc61612.tar.gz bcm5719-llvm-e738efc95b18d328ad796225fd8d8785afc61612.zip | |
[mips] Refactor LUI instruction.
llvm-svn: 170944
Diffstat (limited to 'llvm/lib/Target/Mips')
| -rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrFormats.td | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 9 |
3 files changed, 17 insertions, 6 deletions
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index b2a0d07b6c0..c37f61862b3 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -94,7 +94,7 @@ def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64Regs, immZExt16, or>, ADDI_FM<0xd>; def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64Regs, immZExt16, xor>, ADDI_FM<0xe>; -def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>; +def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM; /// Arithmetic Instructions (3-Operand, R-Type) def DADD : ArithLogicR<"dadd", CPU64Regs>, ADD_FM<0, 0x2c>; diff --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td index 8dad6c222b8..c20c8bdb995 100644 --- a/llvm/lib/Target/Mips/MipsInstrFormats.td +++ b/llvm/lib/Target/Mips/MipsInstrFormats.td @@ -356,6 +356,18 @@ class CLO_FM<bits<6> funct> { let rt = rd; } +class LUI_FM { + bits<5> rt; + bits<16> imm16; + + bits<32> Inst; + + let Inst{31-26} = 0xf; + let Inst{25-21} = 0; + let Inst{20-16} = rt; + let Inst{15-0} = imm16; +} + //===----------------------------------------------------------------------===// // // FLOATING POINT INSTRUCTION FORMATS diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 6d33bdf0136..07e4abd519f 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -388,10 +388,9 @@ class shift_rotate_reg<string opstr, SDNode OpNode, RegisterClass RC>: [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>; // Load Upper Imediate -class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>: - FI<op, (outs RC:$rt), (ins Imm:$imm16), - !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu>, IsAsCheapAsAMove { - let rs = 0; +class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: + InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), + [], IIAlu, FrmI>, IsAsCheapAsAMove { let neverHasSideEffects = 1; let isReMaterializable = 1; } @@ -846,7 +845,7 @@ def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>; def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>; def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>; -def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; +def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; /// Arithmetic Instructions (3-Operand, R-Type) def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>; |
