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* Add patterns for matching immediates whose lower 16-bit is cleared. TheseAkira Hatanaka2011-12-192-0/+10
| | | | | | patterns emit a single LUi instruction instead of a pair of LUi and ORi. llvm-svn: 146900
* Tidy up. Simplify logic. No functional change intended.Akira Hatanaka2011-12-1910-132/+117
| | | | llvm-svn: 146896
* Remove definitions of double word shift plus 32 instructions. Assembler orAkira Hatanaka2011-12-191-21/+9
| | | | | | | direct-object emitter should emit the appropriate shift instruction depending on the shift amount. llvm-svn: 146893
* Remove unused predicate.Akira Hatanaka2011-12-191-3/+0
| | | | llvm-svn: 146889
* Remove the restriction on the first operand of the add node in SelectAddr.Akira Hatanaka2011-12-191-3/+1
| | | | | | | | | | | | | | | | | | This change reduces the number of instructions generated. For example, (load (add (sub $n0, $n1), (MipsLo got(s)))) results in the following sequence of instructions: 1. sub $n2, $n0, $n1 2. lw got(s)($n2) Previously, three instructions were needed. 1. sub $n2, $n0, $n1 2. addiu $n3, $n2, got(s) 3. lw 0($n3) llvm-svn: 146888
* Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct objectAkira Hatanaka2011-12-144-6/+32
| | | | | | | emission is not supported yet, but a patch that adds the support should follow soon. llvm-svn: 146572
* Expand .cprestore directive to multiple instructions if the offset does not fit Akira Hatanaka2011-12-133-16/+35
| | | | | | in a 16-bit field. llvm-svn: 146469
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. llvm-svn: 146466
* LLVMBuild: Introduce a common section which currently has a list of theDaniel Dunbar2011-12-121-0/+3
| | | | | | | | | | | subdirectories to traverse into. - Originally I wanted to avoid this and just autoscan, but this has one key flaw in that new subdirectories can not automatically trigger a rerun of the llvm-build tool. This is particularly a pain when switching back and forth between trees where one has added a subdirectory, as the dependencies will tend to be wrong. This will also eliminates FIXME implicitly. llvm-svn: 146436
* Emit B (unconditional branch) when -relocation-model=pic and J (jump) whenAkira Hatanaka2011-12-123-8/+25
| | | | | | -relocation-model=static. llvm-svn: 146432
* Fix indentation.Akira Hatanaka2011-12-121-1/+1
| | | | llvm-svn: 146431
* LLVMBuild: Remove trailing newline, which irked me.Daniel Dunbar2011-12-124-4/+0
| | | | llvm-svn: 146409
* Mips: Don't create a dangling IR function just to get the address of a symbol.Benjamin Kramer2011-12-111-6/+1
| | | | llvm-svn: 146340
* Rename WrapperPIC. It is now used for both pic and static.Akira Hatanaka2011-12-095-25/+25
| | | | llvm-svn: 146232
* jalr should use t9 ($25) for indirect calls regardless of the relocation modelAkira Hatanaka2011-12-091-4/+8
| | | | | | specified. llvm-svn: 146229
* Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo inAkira Hatanaka2011-12-081-4/+11
| | | | | | | | MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the target is Mips64. llvm-svn: 146183
* Implement 64-bit support for thread local storage handling.Akira Hatanaka2011-12-085-55/+51
| | | | | | | | | | - Modify lowering of global TLS address nodes. - Modify isel of ThreadPointer. - Wrap target global TLS address nodes that are operands of loads with WrapperPIC. - Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be substituted with other existing nodes. llvm-svn: 146175
* Modify class ReadHardware and add definition of 64-bit version of instructionAkira Hatanaka2011-12-072-3/+6
| | | | | | RDHWR. llvm-svn: 146101
* Add newline.Akira Hatanaka2011-12-071-1/+2
| | | | llvm-svn: 146100
* Add 64-bit HWR29 register.Akira Hatanaka2011-12-071-0/+2
| | | | llvm-svn: 146099
* 32 to 64-bit anyext pattern.Akira Hatanaka2011-12-071-0/+4
| | | | llvm-svn: 146097
* 32 to 64-bit zext pattern.Akira Hatanaka2011-12-071-0/+5
| | | | llvm-svn: 146096
* Variable cleanup. Based on past patch submittals variable names haveBruno Cardoso Lopes2011-12-072-55/+60
| | | | | | | been normalized and more descriptive comments added. Patch by Reed Kotler and Jack Carter. llvm-svn: 146088
* 64-bit WrapperPICPat patterns.Akira Hatanaka2011-12-071-0/+6
| | | | llvm-svn: 146086
* Define base class for WrapperPICPat.Akira Hatanaka2011-12-071-7/+7
| | | | llvm-svn: 146081
* Modify LowerFCOPYSIGN to handle Mips64.Akira Hatanaka2011-12-071-14/+22
| | | | llvm-svn: 146080
* Fix comment.Akira Hatanaka2011-12-071-2/+1
| | | | llvm-svn: 146063
* Fix comment.Akira Hatanaka2011-12-071-1/+1
| | | | llvm-svn: 146062
* Fix 64-bit immediate patterns.Akira Hatanaka2011-12-073-6/+25
| | | | llvm-svn: 146059
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-073-12/+11
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Add a few moreLocal/Global R_MIPS_GOT related fixups andBruno Cardoso Lopes2011-12-077-47/+46
| | | | | | | | make the addend fixup code a bit more generic Patch by Jack Carter. llvm-svn: 145998
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-1/+1
| | | | | | | | | 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs llvm-svn: 145975
* Use branches instead of jumps + variable cleanup. Testcase coming next. ↵Bruno Cardoso Lopes2011-12-063-41/+39
| | | | | | Patch by Jack Carter llvm-svn: 145912
* Add register HWR29 numbering. Patch by Jack CarterBruno Cardoso Lopes2011-12-062-0/+2
| | | | llvm-svn: 145910
* MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc.NAKAMURA Takumi2011-12-061-0/+1
| | | | llvm-svn: 145894
* Move target-specific logic out of generic MCAssembler.Jim Grosbach2011-12-061-0/+10
| | | | | | | | Whether a fixup needs relaxation for the associated instruction is a target-specific function, as the FIXME indicated. Create a hook for that and use it. llvm-svn: 145881
* Add definitions of 64-bit extract and insert instrucions and makeAkira Hatanaka2011-12-052-12/+17
| | | | | | | PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
* Split ExtIns into two base classes and have instructions EXT and INS derive fromAkira Hatanaka2011-12-051-17/+21
| | | | | | them. llvm-svn: 145852
* Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 andAkira Hatanaka2011-12-051-20/+16
| | | | | | O32 with relocation-model=pic too. llvm-svn: 145850
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-023-32/+33
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Change names for MIPS "generic" processors defined in Mips.td to match what GNUAkira Hatanaka2011-11-292-4/+4
| | | | | | | | | | tools use. Patch by Simon Atanasyan. "mips32r1" => "mips32" "4ke" => mips32r2" "mips64r1" => "mips64" llvm-svn: 145451
* build/CMake: Finish removal of add_llvm_library_dependencies.Daniel Dunbar2011-11-294-31/+0
| | | | llvm-svn: 145420
* This patch makes the following changes necessary for MIPS' direct code emission.Akira Hatanaka2011-11-236-55/+236
| | | | | | | | - lower unaligned loads/stores. - encode the size operand of instructions INS and EXT. - emit relocation information needed for JAL (jump-and-link). llvm-svn: 145113
* This patch addresses gp relative fixups/relocations for jump tables.Akira Hatanaka2011-11-231-1/+7
| | | | llvm-svn: 145112
* Lower 64-bit constant pool node.Akira Hatanaka2011-11-161-8/+12
| | | | llvm-svn: 144849
* Lower 64-bit block address.Akira Hatanaka2011-11-161-9/+11
| | | | llvm-svn: 144847
* Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpoolAkira Hatanaka2011-11-162-7/+24
| | | | | | nodes. llvm-svn: 144841
* 64-bit jump register instruction.Akira Hatanaka2011-11-162-6/+7
| | | | llvm-svn: 144840
* Sink codegen optimization level into MCCodeGenInfo along side relocation modelEvan Cheng2011-11-163-29/+35
| | | | | | | and code model. This eliminates the need to pass OptLevel flag all over the place and makes it possible for any codegen pass to use this information. llvm-svn: 144788
* Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bitAkira Hatanaka2011-11-152-18/+24
| | | | | | registers and instructions when ABI is N64. llvm-svn: 144666
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