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authorAkira Hatanaka <ahatanaka@mips.com>2011-12-07 23:21:19 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2011-12-07 23:21:19 +0000
commit9778e7a67c5ebb6a36d84b0080cb1a4f039888e6 (patch)
treee1c4f7f886e337671ee777eddccc1b59644538c4 /llvm/lib/Target/Mips
parentae378af6670660395de018c271d192fd66914eb8 (diff)
downloadbcm5719-llvm-9778e7a67c5ebb6a36d84b0080cb1a4f039888e6.tar.gz
bcm5719-llvm-9778e7a67c5ebb6a36d84b0080cb1a4f039888e6.zip
32 to 64-bit anyext pattern.
llvm-svn: 146097
Diffstat (limited to 'llvm/lib/Target/Mips')
-rw-r--r--llvm/lib/Target/Mips/Mips64InstrInfo.td4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td
index 91c91022fd8..301905b0361 100644
--- a/llvm/lib/Target/Mips/Mips64InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -225,6 +225,9 @@ def DINS : InsBase<7, "dins", CPU64Regs>;
def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
"dsll32\t$rd, $rt, 0", [], IIAlu>;
+def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
+ "sll\t$rd, $rt, 0", [], IIAlu>;
+
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
@@ -300,4 +303,5 @@ def : Pat<(i32 (trunc CPU64Regs:$src)),
(SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>;
// 32-to-64-bit extension
+def : Pat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
def : Pat<(i64 (zext CPURegs:$src)), (DSRL32 (DSLL64_32 CPURegs:$src), 0)>;
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