summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Mips/MipsSubtarget.cpp
Commit message (Collapse)AuthorAgeFilesLines
* [mips][micromips] Initial support for micrmomips DSP instructions and ↵Zoran Jovanovic2015-10-121-2/+2
| | | | | | | | addu.qb implementation Differential Revision: http://reviews.llvm.org/D12798 llvm-svn: 250058
* Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and ↵Daniel Sanders2015-09-151-12/+11
| | | | | | | | related. NFC. Eric has replied and has demanded the patch be reverted. llvm-svn: 247702
* Re-commit r247683: Replace Triple with a new TargetTuple in MCTargetDesc/* ↵Daniel Sanders2015-09-151-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | and related. NFC. Summary: This is the first patch in the series to migrate Triple's (which are ambiguous) to TargetTuple's (which aren't). For the moment, TargetTuple simply passes all requests to the Triple object it holds. Once it has replaced Triple, it will start to implement the interface in a more suitable way. This change makes some changes to the public C++ API. In particular, InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer() now take TargetTuples instead of Triples. The other public C++ API's have been left as-is for the moment to reduce patch size. This commit also contains a trivial patch to clang to account for the C++ API change. Thanks go to Pavel Labath for fixing LLDB for me. Reviewers: rengolin Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10969 llvm-svn: 247692
* Revert r247684 - Replace Triple with a new TargetTuple ...Daniel Sanders2015-09-151-12/+11
| | | | | | LLDB needs to be updated in the same commit. llvm-svn: 247686
* Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.Daniel Sanders2015-09-151-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the first patch in the series to migrate Triple's (which are ambiguous) to TargetTuple's (which aren't). For the moment, TargetTuple simply passes all requests to the Triple object it holds. Once it has replaced Triple, it will start to implement the interface in a more suitable way. This change makes some changes to the public C++ API. In particular, InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer() now take TargetTuples instead of Triples. The other public C++ API's have been left as-is for the moment to reduce patch size. This commit also contains a trivial patch to clang to account for the C++ API change. Reviewers: rengolin Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10969 llvm-svn: 247683
* [mips] Added support for various EVA ASE instructions.Daniel Sanders2015-09-151-1/+2
| | | | | | | | | | | | | | | | | | | | Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 llvm-svn: 247669
* [mips] Added support for the div, divu, ddiv and ddivu macros which use ↵Daniel Sanders2015-09-031-1/+1
| | | | | | | | | | | | | | | | traps and breaks in the integrated assembler. Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
* Remove getDataLayout() from TargetSelectionDAGInfo (had no users)Mehdi Amini2015-07-091-1/+1
| | | | | | | | | | | | | | | | | | Summary: Remove empty subclass in the process. This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, llvm-commits, rafael, yaron.keren, ted Differential Revision: http://reviews.llvm.org/D11045 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241780
* Clean up redundant copies of Triple objects. NFCDaniel Sanders2015-06-161-2/+1
| | | | | | | | | | | | | | Summary: Reviewers: rengolin Reviewed By: rengolin Subscribers: llvm-commits, rengolin, jholewinski Differential Revision: http://reviews.llvm.org/D10382 llvm-svn: 239823
* Rename TargetSubtargetInfo::enablePostMachineScheduler() to ↵Matthias Braun2015-06-131-1/+1
| | | | | | | | | | | | | | enablePostRAScheduler() r213101 changed the behaviour of this method to not only affect the PostMachineScheduler scheduler but also the PostRAScheduler scheduler, renaming should make this fact clear. Also document that the preferred way is to specify this in the scheduling model instead of overriding this method. Differential Revision: http://reviews.llvm.org/D10427 llvm-svn: 239659
* Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and ↵Daniel Sanders2015-06-101-2/+3
| | | | | | | | | | | | | | | | | | create*MCSubtargetInfo(). NFC. Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: rafael Reviewed By: rafael Subscribers: rafael, ted, jfb, llvm-commits, rengolin, jholewinski Differential Revision: http://reviews.llvm.org/D10311 llvm-svn: 239467
* [mips] Add the SoftFloat MipsSubtarget feature.Toma Tabacu2015-05-071-10/+6
| | | | | | | | | | | | | | Summary: This will enable the IAS to reject floating point instructions if soft-float is enabled. Reviewers: dsanders, echristo Reviewed By: dsanders Subscribers: jfb, llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9053 llvm-svn: 236713
* Fix wording and grammar in Mips subtarget options.Eric Christopher2015-02-201-23/+18
| | | | llvm-svn: 230001
* Unify selectMipsCPU implementations.Eric Christopher2015-02-181-14/+2
| | | | llvm-svn: 229595
* Move DataLayout back to the TargetMachine from TargetSubtargetInfoEric Christopher2015-01-261-33/+3
| | | | | | | | | | | | | | | | | | | derived classes. Since global data alignment, layout, and mangling is often based on the DataLayout, move it to the TargetMachine. This ensures that global data is going to be layed out and mangled consistently if the subtarget changes on a per function basis. Prior to this all targets(*) have had subtarget dependent code moved out and onto the TargetMachine. *One target hasn't been migrated as part of this change: R600. The R600 port has, as a subtarget feature, the size of pointers and this affects global data layout. I've currently hacked in a FIXME to enable progress, but the port needs to be updated to either pass the 64-bitness to the TargetMachine, or fix the DataLayout to avoid subtarget dependent features. llvm-svn: 227113
* Move the Mips target to storing the ABI in the TargetMachine ratherEric Christopher2015-01-261-24/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | than on MipsSubtargetInfo. This required a bit of massaging in the MC level to handle this since MC is a) largely a collection of disparate classes with no hierarchy, and b) there's no overarching equivalent to the TargetMachine, instead only the subtarget via MCSubtargetInfo (which is the base class of TargetSubtargetInfo). We're now storing the ABI in both the TargetMachine level and in the MC level because the AsmParser and the TargetStreamer both need to know what ABI we have to parse assembly and emit objects. The target streamer has a pointer to the one in the asm parser and is updated when the asm parser is created. This is fragile as the FIXME comment notes, but shouldn't be a problem in practice since we always create an asm parser before attempting to emit object code via the assembler. The TargetMachine now contains the ABI so that the DataLayout can be constructed dependent upon ABI. All testcases have been updated to use the -target-abi command line flag so that we can set the ABI without using a subtarget feature. Should be no change visible externally here. llvm-svn: 227102
* Make the TargetMachine in MipsSubtarget a reference ratherEric Christopher2015-01-081-8/+8
| | | | | | than a pointer to make unifying code a bit easier. llvm-svn: 225459
* Remove unused variable, initializer, and accessor.Eric Christopher2014-12-191-9/+4
| | | | llvm-svn: 224650
* [mips] Enable code generation for MIPS-III.Vasileios Kalintiris2014-12-121-6/+2
| | | | | | | | | | | | | | | | | | Summary: This commit enables the MIPS-III target and adds support for code generation of SELECT nodes. We have to use pseudo-instructions with custom inserters for these nodes as MIPS-III CPUs do not have conditional-move instructions. Depends on D6212 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6464 llvm-svn: 224128
* [mips] Add preliminary support for the MIPS II target.Vasileios Kalintiris2014-11-111-5/+6
| | | | | | | | | | | | | | | | | | | Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
* [mips] Add the following MIPS options that control gp-relative addressing ofSasa Stankovic2014-11-061-3/+13
| | | | | | | | | small data items: -mgpopt, -mlocal-sdata, -mextern-sdata. Implement gp-relative addressing for constants. Differential Revision: http://reviews.llvm.org/D4903 llvm-svn: 221450
* [mips] Replace MipsABIEnum with a MipsABIInfo class.Daniel Sanders2014-10-241-2/+2
| | | | | | | | | | | | | | | | | | | | | Summary: No functional change yet, it's just an object replacement for an enum. It will allow us to gather ABI information in a single place so that we can start testing for properties of the ABI's instead of the ABI itself. For example we will eventually be able to use: ABI.MinStackAlignmentInBytes() instead of: (isABI_N32() || isABI_N64()) ? 16 : 8 which is clearer and more maintainable. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3341 llvm-svn: 220568
* constify the TargetMachine being passed through the Mips subtargetEric Christopher2014-09-191-1/+1
| | | | | | creation. llvm-svn: 218169
* Reinstate "Nuke the old JIT."Eric Christopher2014-09-021-1/+1
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* [mips] Invert the abicalls feature bit to be noabicalls so that it's ↵Daniel Sanders2014-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | possible for -mno-abicalls to take effect. Also added the testcase that should have been in r215194. This behaviour has surprised me a few times now. The problem is that the generated MipsSubtarget::ParseSubtargetFeatures() contains code like this: if ((Bits & Mips::FeatureABICalls) != 0) IsABICalls = true; so '-abicalls' means 'leave it at the default' and '+abicalls' means 'set it to true'. In this case, (and the similar -modd-spreg case) I'd like the code to be IsABICalls = (Bits & Mips::FeatureABICalls) != 0; or possibly: if ((Bits & Mips::FeatureABICalls) != 0) IsABICalls = true; else IsABICalls = false; and preferably arrange for 'Bits & Mips::FeatureABICalls' to be true by default (on some triples). llvm-svn: 215211
* [mips] Initial implementation of -mabicalls/-mno-abicalls.Daniel Sanders2014-08-081-6/+7
| | | | | | | | | | | This patch implements the main rules for -mno-abicalls such as reserving $gp, and emitting the correct .option directive. Patch by Matheus Almeida and Toma Tabacu Differential Revision: http://reviews.llvm.org/D4231 llvm-svn: 215194
* Temporarily Revert "Nuke the old JIT." as it's not quite ready toEric Christopher2014-08-071-1/+1
| | | | | | | | | | | be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 215154
* Nuke the old JIT.Rafael Espindola2014-08-071-1/+1
| | | | | | | | | I am sure we will be finding bits and pieces of dead code for years to come, but this is a good start. Thanks to Lang Hames for making MCJIT a good replacement! llvm-svn: 215111
* Fundamentally change the MipsSubtarget replacement machinery:Eric Christopher2014-07-181-81/+1
| | | | | | | | | | | | | | | | | a) Move the replacement level decision to the target machine. b) Create additional subtargets at the TargetMachine level to cache and make replacement easy. c) Make the mips16 features obvious. d) Remove the override logic as it no longer does anything. e) Have MipsModuleDAGToDAGISel take only the target machine. f) Have the constant islands pass grab the current subtarget from the MachineFunction (via the TargetMachine) instead of caching it. g) Unconditionally initialize TLOF. h) Remove the old complicated subtarget based resetting and replace it with simple conditionals. llvm-svn: 213430
* FrameLowering depends only upon the Subtarget, so only take a subtargetEric Christopher2014-07-181-3/+3
| | | | | | during initialization. llvm-svn: 213429
* In preparation for replacing the whole subtarget on the target machine,Eric Christopher2014-07-181-3/+3
| | | | | | have target lowering take the subtarget explicitly. llvm-svn: 213426
* Make InstrInfo depend only upon the Subtarget getting passed inEric Christopher2014-07-181-3/+3
| | | | | | rather than the TargetMachine. llvm-svn: 213425
* Avoid caching the relocation model on the subtarget, this is forEric Christopher2014-07-181-4/+7
| | | | | | | | | | | two reasons: a) we're already caching the target machine which contains it, b) which relocation model you get is dependent upon whether or not you ask before MCCodeGenInfo is constructed on the target machine, so avoid any latent issues there. llvm-svn: 213420
* Avoid resetting the UseSoftFloat and FloatABIType on the TargetMachineEric Christopher2014-07-181-9/+2
| | | | | | | | | | Options struct and move the comment to inMips16HardFloat. Use the fact that we now know whether or not we cared about soft float to set the libcalls. Accordingly rename mipsSEUsesSoftFloat to abiUsesSoftFloat and propagate since it's no longer CPU specific. llvm-svn: 213335
* Move Post RA Scheduling flag bit into SchedMachineModelSanjay Patel2014-07-151-8/+10
| | | | | | | | | | | | | | | | | | | | | Refactoring; no functional changes intended Removed PostRAScheduler bits from subtargets (X86, ARM). Added PostRAScheduler bit to MCSchedModel class. This bit is set by a CPU's scheduling model (if it exists). Removed enablePostRAScheduler() function from TargetSubtargetInfo and subclasses. Fixed the existing enablePostMachineScheduler() method to use the MCSchedModel (was just returning false!). Added methods to TargetSubtargetInfo to allow overrides for AntiDepBreakMode, CriticalPathRCs, and OptLevel for PostRAScheduling. Added enablePostRAScheduler() function to PostRAScheduler class which queries the subtarget for the above values. Preserved existing scheduler behavior for ARM, MIPS, PPC, and X86: a. ARM overrides the CPU's postRA settings by enabling postRA for any non-Thumb or Thumb2 subtarget. b. MIPS overrides the CPU's postRA settings by enabling postRA for everything. c. PPC overrides the CPU's postRA settings by enabling postRA for everything. d. X86 is the only target that actually has postRA specified via sched model info. Differential Revision: http://reviews.llvm.org/D4217 llvm-svn: 213101
* [mips] For the FP64A ABI, odd-numbered double-precision moves must not use ↵Daniel Sanders2014-07-141-3/+1
| | | | | | | | | | | | | | | | | | | | | mtc1/mfc1. Summary: This is because the FP64A the hardware will redirect 32-bit reads/writes from/to odd-numbered registers to the upper 32-bits of the corresponding even register. In effect, simulating FR=0 mode when FR=0 mode is not available. Unfortunately, we have to make the decision to avoid mfc1/mtc1 before register allocation so we currently do this for even registers too. FPXX has a similar requirement on 32-bit architectures that lack mfhc1/mthc1 so this patch also handles the affected moves from the FPU for FPXX too. Moves to the FPU were supported by an earlier commit. Differential Revision: http://reviews.llvm.org/D4484 llvm-svn: 212938
* [mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI isSasa Stankovic2014-07-141-0/+3
| | | | | | | | | | | | | | | enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1) This prevents the upper 32-bits of a double precision value from being moved to the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure that the code generated executes correctly regardless of the current FPU mode. MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue to use dmtc1. Differential Revision: http://reviews.llvm.org/D4465 llvm-svn: 212930
* [mips] Added FPXX modeless calling convention.Zoran Jovanovic2014-07-101-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D4293 llvm-svn: 212726
* [mips] Add support for -modd-spreg/-mno-odd-spregDaniel Sanders2014-07-101-7/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When -mno-odd-spreg is in effect, 32-bit floating point values are not permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit floating point comparison results from being written to odd registers. This option has three purposes: * It allows support for certain MIPS implementations such as loongson-3a that do not allow the use of odd registers for single precision arithmetic. * When using -mfpxx, -mno-odd-spreg is the default and this allows us to statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1 instructions to/from odd registers are guaranteed not to appear for any reason. Once this has been established, the user can then re-enable -modd-spreg to regain the use of all 32 single-precision registers. * When using -mfp64 and -mno-odd-spreg together, an O32 extension named O32 FP64A is used as the ABI. This is intended to provide almost all functionality of an FR=1 processor but can also be executed on a FR=0 core with the assistance of a hardware compatibility mode which emulates FR=0 behaviour on an FR=1 processor. * Added '.module oddspreg' and '.module nooddspreg' each of which update the .MIPS.abiflags section appropriately * Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller doesn't have to remember to do it. * MipsABIFlags now calculates the flags1 and flags2 member on demand rather than trying to maintain them in the same format they will be emitted in. There is one portion of the -mfp64 and -mno-odd-spreg combination that is not implemented yet. Moves to/from odd-numbered double-precision registers must not use mtc1. I will fix this in a follow-up. Differential Revision: http://reviews.llvm.org/D4383 llvm-svn: 212717
* Move subtarget dependent features into the subtarget from the targetEric Christopher2014-07-031-18/+58
| | | | | | | machine. Includes a fix for a subtarget initialization for hard floating point on mips16. llvm-svn: 212240
* Move the data layout and selection dag info from the mips target machineEric Christopher2014-07-021-3/+33
| | | | | | down to the subtarget. llvm-svn: 212224
* Break out subtarget initialization that dependent variables need intoEric Christopher2014-07-021-11/+15
| | | | | | a separate function and clean up calling convention for helper function. llvm-svn: 212153
* Unify these two lines.Eric Christopher2014-07-021-2/+1
| | | | llvm-svn: 212152
* Move MipsJITInfo to the subtarget rather than the target machine.Eric Christopher2014-07-021-1/+1
| | | | llvm-svn: 212151
* [mips] Marked up instructions added in MIPS32r2 and tested that IAS for ↵Daniel Sanders2014-05-131-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
* [mips] Marked up instructions added in MIPS-V and tested that IAS for ↵Daniel Sanders2014-05-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | -mcpu=mips[1234] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-V that was available in MIPS32R2 Most of these instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. It happens because many of the MIPS V instructions have not been implemented. Depends on D3694 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3695 llvm-svn: 208546
* [mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64Daniel Sanders2014-05-121-4/+1
| | | | | | | | | | | | | | | | | | | | | Summary: DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no effect on the CodeGen tests since expansion of i64 prevented their use anyway. The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as well. This is not a functional change since DCLZ is still prohibited by being a MIPS64 instruction (MIPS16 is only compatible with MIPS32). No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3694 llvm-svn: 208544
* [mips] Fold FeatureSEInReg into FeatureMips32r2Daniel Sanders2014-05-121-5/+5
| | | | | | | | | | | | Summary: No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3693 llvm-svn: 208543
* [mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2Daniel Sanders2014-05-121-6/+5
| | | | | | | | | | | | | | | | | Summary: dsbh and dshd are not available on Mips32r2. No codegen test changes required since expansion of i64 prevented the use of these instructions anyway. Depends on D3690 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3692 llvm-svn: 208542
* [mips] Replace FeatureFPIdx with FeatureMips4_32r2Daniel Sanders2014-05-121-5/+6
| | | | | | | | | | | | | | | | | Summary: No functional change. The minor change to the MIPS16 code is in preparation for a patch that will handle 32-bit FPIdx instructions separately to 64-bit (because they were added in different revisions) Depends on D3677 Reviewers: rkotler, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3690 llvm-svn: 208541
OpenPOWER on IntegriCloud