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authorVasileios Kalintiris <Vasileios.Kalintiris@imgtec.com>2014-11-11 11:43:55 +0000
committerVasileios Kalintiris <Vasileios.Kalintiris@imgtec.com>2014-11-11 11:43:55 +0000
commitb2dd15f8c702f03c9f01e9af17742d68c745f424 (patch)
tree214b04662ed7e296141d38d6a5adc2d0a0066a6a /llvm/lib/Target/Mips/MipsSubtarget.cpp
parent8c1c95e95c25d85943deb6506ee7cfe6863d3659 (diff)
downloadbcm5719-llvm-b2dd15f8c702f03c9f01e9af17742d68c745f424.tar.gz
bcm5719-llvm-b2dd15f8c702f03c9f01e9af17742d68c745f424.zip
[mips] Add preliminary support for the MIPS II target.
Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSubtarget.cpp')
-rw-r--r--llvm/lib/Target/Mips/MipsSubtarget.cpp11
1 files changed, 6 insertions, 5 deletions
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index ab8c03a1c50..8768b12f7d1 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -109,7 +109,7 @@ static std::string computeDataLayout(const MipsSubtarget &ST) {
MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool little,
const MipsTargetMachine *_TM)
- : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
+ : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
ABI(MipsABIInfo::Unknown()), IsLittle(little), IsSingleFloat(false),
IsFPXX(false), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
@@ -126,13 +126,14 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
PreviousInMips16Mode = InMips16Mode;
- // Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
- // MIPS-V. They have not been tested and currently exist for the integrated
+ if (MipsArchVersion == MipsDefault)
+ MipsArchVersion = Mips32;
+
+ // Don't even attempt to generate code for MIPS-I, MIPS-III and MIPS-V.
+ // They have not been tested and currently exist for the integrated
// assembler only.
if (MipsArchVersion == Mips1)
report_fatal_error("Code generation for MIPS-I is not implemented", false);
- if (MipsArchVersion == Mips2)
- report_fatal_error("Code generation for MIPS-II is not implemented", false);
if (MipsArchVersion == Mips3)
report_fatal_error("Code generation for MIPS-III is not implemented",
false);
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