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* Re-commit r221056 and others with fix, "[mips] Move F128 argument handling ↵Daniel Sanders2014-11-021-3/+3
| | | | | | | | | into MipsCCState as we did for returns. NFC." sret arguments can never originate from an f128 argument so we detect sret arguments and push false into OriginalArgWasF128. llvm-svn: 221102
* Revert r221056 and others, "[mips] Move F128 argument handling into ↵NAKAMURA Takumi2014-11-021-3/+3
| | | | | | | | | | | | | MipsCCState as we did for returns. NFC." r221056 "[mips] Move F128 argument handling into MipsCCState as we did for returns. NFC." r221058 "[mips] Fix unused variable warning introduced in r221056" r221059 "[mips] Move all ByVal handling into CCState and tablegen-erated code. NFC." r221061 "Renamed CCState members that appear to misspell 'Processed' as 'Proceed'. NFC." It cuased an undefined behavior in LLVM :: CodeGen/Mips/return-vector.ll. llvm-svn: 221081
* [mips] Move all ByVal handling into CCState and tablegen-erated code. NFC.Daniel Sanders2014-11-011-3/+3
| | | | | | | | | | | | | | | | | Summary: CCState already contains a byval implementation that is very similar to the Mips custom code. This patch merges the custom code into the existing common code and tablegen-erated code. Reviewers: vmedic Reviewed By: vmedic Subscribers: rnk, llvm-commits Differential Revision: http://reviews.llvm.org/D5977 llvm-svn: 221059
* [mips] For indirect calls we don't need $gp to point to .got. Mips linkerSasa Stankovic2014-10-011-1/+1
| | | | | | | | | doesn't generate lazy binding stub for a function whose address is taken in the program. Differential Revision: http://reviews.llvm.org/D5067 llvm-svn: 218744
* constify the TargetMachine being passed through the Mips subtargetEric Christopher2014-09-191-1/+1
| | | | | | creation. llvm-svn: 218169
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-3/+3
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Add alignment value to allowsUnalignedMemoryAccessMatt Arsenault2014-07-271-2/+3
| | | | | | | | | | Rename to allowsMisalignedMemoryAccess. On R600, 8 and 16 byte accesses are mostly OK with 4-byte alignment, and don't need to be split into multiple accesses. Vector loads with an alignment of the element type are not uncommon in OpenCL code. llvm-svn: 214055
* In preparation for replacing the whole subtarget on the target machine,Eric Christopher2014-07-181-1/+2
| | | | | | have target lowering take the subtarget explicitly. llvm-svn: 213426
* Make these preprocessor directives match all of the others in the port.Eric Christopher2014-07-031-2/+2
| | | | llvm-svn: 212245
* So that we can include target lowering in the subtarget, remove includeEric Christopher2014-07-021-7/+1
| | | | | | | circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
* [mips][msa] Fix vector insertions where the index is variableDaniel Sanders2014-04-301-0/+5
| | | | | | | | | | | | | | | | | | | | | Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-13/+14
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
* [C++] Use 'nullptr'.Craig Topper2014-04-281-2/+2
| | | | llvm-svn: 207394
* Switch all uses of LLVM_OVERRIDE to just use 'override' directly.Craig Topper2014-03-021-3/+2
| | | | llvm-svn: 202621
* Add address space argument to allowsUnalignedMemoryAccess.Matt Arsenault2014-02-051-1/+3
| | | | | | | On R600, some address spaces have more strict alignment requirements than others. llvm-svn: 200887
* [mips][msa] Added support for matching fexp2 from normal IR (i.e. not ↵Daniel Sanders2013-10-231-0/+6
| | | | | | intrinsics) llvm-svn: 193239
* [mips][msa] Added support for build_vector for v4f32 and v2f64.Daniel Sanders2013-10-151-0/+6
| | | | llvm-svn: 192699
* [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.Daniel Sanders2013-09-271-0/+6
| | | | | | | For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. llvm-svn: 191515
* [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64Daniel Sanders2013-09-271-0/+6
| | | | | | | For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. llvm-svn: 191514
* [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-241-0/+3
| | | | llvm-svn: 191301
* [mips][msa] Added support for matching insert and copy from normal IR (i.e. ↵Daniel Sanders2013-09-231-0/+1
| | | | | | | | | | | not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
* [mips][msa] Implemented build_vector using ldi, fill, and custom ↵Daniel Sanders2013-09-231-0/+5
| | | | | | | | | | | | | | | | | | SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal llvm-svn: 191191
* [mips][msa] Separate the configuration of int/float vector types since they ↵Daniel Sanders2013-09-111-1/+3
| | | | | | | | will diverge soon No functional change llvm-svn: 190506
* [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index doubleAkira Hatanaka2013-09-071-0/+3
| | | | | | | | | | precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
* [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.vDaniel Sanders2013-08-281-0/+3
| | | | | | | | | | | | | These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
* [mips][msa] Added load/store intrinsics.Daniel Sanders2013-08-281-0/+1
| | | | llvm-svn: 189476
* [mips][msa] Split MSA128 regset into size-specific sets containing the same ↵Daniel Sanders2013-08-231-1/+1
| | | | | | registers. llvm-svn: 189095
* [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)Jack Carter2013-08-151-0/+2
| | | | | | | | | | | | | Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
* [mips] Rename accumulator register classes and FP register operands.Akira Hatanaka2013-08-081-2/+2
| | | | llvm-svn: 188020
* [mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN andAkira Hatanaka2013-04-131-0/+3
| | | | | | | | lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering. No functionality changes. llvm-svn: 179444
* [mips] Override TargetLoweringBase::isShuffleMaskLegal.Akira Hatanaka2013-04-131-0/+5
| | | | llvm-svn: 179433
* [mips] Move the code which does dag-combine for multiply-add/sub nodes toAkira Hatanaka2013-03-301-0/+2
| | | | | | | | | derived class MipsSETargetLowering. We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16 doesn't have support for multipy-add/sub instructions. llvm-svn: 178404
* [mips] Fix definitions of multiply, multiply-add/sub and divide instructions.Akira Hatanaka2013-03-301-0/+5
| | | | | | | | | The new instructions have explicit register output operands and use table-gen patterns instead of C++ code to do instruction selection. Mips16's instructions are unaffected by this change. llvm-svn: 178403
* [mips] Implement getRepRegClassFor in MipsSETargetLowering. This function isAkira Hatanaka2013-03-301-0/+9
| | | | | | called in several places in ScheduleDAGRRList.cpp. llvm-svn: 178393
* [mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is forAkira Hatanaka2013-03-131-0/+46
mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
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