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| author | Craig Topper <craig.topper@gmail.com> | 2014-04-29 07:58:02 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2014-04-29 07:58:02 +0000 |
| commit | 56c590af3b4fe68fe3eefd73c6c027c4a9b7314b (patch) | |
| tree | 6587ea65808c3ae10004fe63876fc1f6ec722c2e /llvm/lib/Target/Mips/MipsSEISelLowering.h | |
| parent | 2865c986d160306fd297a276f51ac48e68c95597 (diff) | |
| download | bcm5719-llvm-56c590af3b4fe68fe3eefd73c6c027c4a9b7314b.tar.gz bcm5719-llvm-56c590af3b4fe68fe3eefd73c6c027c4a9b7314b.zip | |
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition
llvm-svn: 207506
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSEISelLowering.h')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSEISelLowering.h | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.h b/llvm/lib/Target/Mips/MipsSEISelLowering.h index 435c15c7503..b88ddea89b8 100644 --- a/llvm/lib/Target/Mips/MipsSEISelLowering.h +++ b/llvm/lib/Target/Mips/MipsSEISelLowering.h @@ -33,19 +33,20 @@ namespace llvm { bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS = 0, bool *Fast = nullptr) const override; - virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; - virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; + SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; - virtual MachineBasicBlock * - EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; + MachineBasicBlock * + EmitInstrWithCustomInserter(MachineInstr *MI, + MachineBasicBlock *MBB) const override; - virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, - EVT VT) const { + bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, + EVT VT) const override { return false; } - virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { + const TargetRegisterClass *getRepRegClassFor(MVT VT) const override { if (VT == MVT::Untyped) return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass; @@ -54,16 +55,16 @@ namespace llvm { } private: - virtual bool - isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, - unsigned NextStackOffset, - const MipsFunctionInfo& FI) const; + bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, + unsigned NextStackOffset, + const MipsFunctionInfo& FI) const override; - virtual void + void getOpndList(SmallVectorImpl<SDValue> &Ops, std::deque< std::pair<unsigned, SDValue> > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, - CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const; + CallLoweringInfo &CLI, SDValue Callee, + SDValue Chain) const override; SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; |

