summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Add #include of raw_ostream.h to MipsSEISelLowering.cppHans Wennborg2013-10-301-0/+1
| | | | | | | | Fixing this Windows build error: ..\lib\Target\Mips\MipsSEISelLowering.cpp(997) : error C2027: use of undefined type 'llvm::raw_ostream' llvm-svn: 193696
* [mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from ↵Daniel Sanders2013-10-301-5/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | normal IR (i.e. not intrinsics) Also corrected the definition of the intrinsics for these instructions (the result register is also the first operand), and added intrinsics for bsel and bseli to clang (they already existed in the backend). These four operations are mostly equivalent to bsel, and bseli (the difference is which operand is tied to the result). As a result some of the tests changed as described below. bitwise.ll: - bsel.v test adapted so that the mask is unknown at compile-time. This stops it emitting bmnzi.b instead of the intended bsel.v. - The bseli.b test now tests the right thing. Namely the case when one of the values is an uimm8, rather than when the condition is a uimm8 (which is covered by bmnzi.b) compare.ll: - bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this is the same operation (see MSA.txt). i8.ll - CHECK-DAG-ized test. - bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands because this is the same operation (see MSA.txt). - bseli.b still emits bseli.b though because the immediate makes it distinguishable from bmnzi.b. vec.ll: - CHECK-DAG-ized test. - bmz.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). - bsel.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). llvm-svn: 193693
* [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. ↵Daniel Sanders2013-10-301-0/+24
| | | | | | | | | | | | | | | | | not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. llvm-svn: 193687
* [mips][msa] Combine binsri-like DAG of AND and OR into equivalent VSELECTDaniel Sanders2013-10-301-0/+108
| | | | | | | | | | | | | | | (or (and $a, $mask), (and $b, $inverse_mask)) => (vselect $mask, $a, $b). where $mask is a constant splat. This allows bitwise operations to make use of bsel. It's also a stepping stone towards matching bins[lr], and bins[lr]i from normal IR. Two sets of similar tests have been added in this commit. The bsel_* functions test the case where binsri cannot be used. The binsr_*_i functions will start to use the binsri instruction in the next commit. llvm-svn: 193682
* [mips] MipsSETargetLowering now reports DAGCombiner changes when using ↵Daniel Sanders2013-10-301-1/+9
| | | | | | | | -debug-only=mips-isel No test since -debug output is intended for developers and not end-users. llvm-svn: 193681
* [mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not ↵Daniel Sanders2013-10-301-0/+11
| | | | | | | | | | intrinsics) splat.d is implemented but this subtest is currently disabled. This is because it is difficult to match the appropriate IR on MIPS32. There is a patch under review that should help with this so I hope to enable the subtest soon. llvm-svn: 193680
* [mips][msa] Added support for matching fexp2 from normal IR (i.e. not ↵Daniel Sanders2013-10-231-0/+70
| | | | | | intrinsics) llvm-svn: 193239
* [mips][msa] Added lsa instructionDaniel Sanders2013-10-171-0/+6
| | | | llvm-svn: 192895
* [mips][msa] Removed ldx.[bhwd] and stx.[bhwd].Daniel Sanders2013-10-171-8/+0
| | | | | | | | These were present in a previous version of the MSA spec but are not present in the published version. There is no hardware that uses these instructions. llvm-svn: 192888
* [mips][msa] Added support for build_vector for v4f32 and v2f64.Daniel Sanders2013-10-151-9/+84
| | | | llvm-svn: 192699
* [mips] Rename isel nodes.Akira Hatanaka2013-10-151-11/+11
| | | | llvm-svn: 192663
* [mips] Delete unnecessary code.Akira Hatanaka2013-10-151-3/+0
| | | | llvm-svn: 192660
* [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from ↵Daniel Sanders2013-10-111-0/+18
| | | | | | normal IR (i.e. not intrinsics) llvm-svn: 192438
* [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not ↵Daniel Sanders2013-10-111-0/+7
| | | | | | intrinsics) llvm-svn: 192435
* [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not ↵Daniel Sanders2013-10-111-0/+5
| | | | | | intrinsics) llvm-svn: 192430
* [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] ↵Daniel Sanders2013-10-111-0/+23
| | | | | | from normal IR (i.e. not intrinsics) llvm-svn: 192429
* [mips] Fix definition of mfhi and mflo instructions to read from the wholeAkira Hatanaka2013-10-071-20/+8
| | | | | | | | | | | | | | | | accumulator instead of its sub-registers, $hi and $lo. We need this change to prevent a mflo following a mtlo from reading an unpredictable/undefined value, as shown in the following example: mult $6, $7 // result of $6 * $7 is written to $lo and $hi. mflo $2 // read lower 32-bit result from $lo. mtlo $4 // write to $lo. the content of $hi becomes unpredictable. mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value. I don't have a test case for this change that reliably reproduces the problem. llvm-svn: 192119
* [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not ↵Daniel Sanders2013-10-011-0/+14
| | | | | | intrinsics) llvm-svn: 191737
* [mips][msa] Implemented insert.d intrinsic.Daniel Sanders2013-09-271-14/+3
| | | | | | | This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is further lowered into a sequence of insert.w's on MIPS32. llvm-svn: 191521
* [mips][msa] Implemented fill.d intrinsic.Daniel Sanders2013-09-271-3/+5
| | | | | | | This intrinsic is lowered into an equivalent BUILD_VECTOR which is further lowered into a sequence of insert.w's on MIPS32. llvm-svn: 191519
* [mips][msa] Implemented copy_[us].d intrinsic.Daniel Sanders2013-09-271-0/+16
| | | | | | | This intrinsic is lowered into equivalent copy_s.w instructions during legalization. llvm-svn: 191518
* [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.Daniel Sanders2013-09-271-0/+59
| | | | | | | For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. llvm-svn: 191515
* [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64Daniel Sanders2013-09-271-4/+83
| | | | | | | For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. llvm-svn: 191514
* [mips][msa] Added support for matching splati from normal IR (i.e. not ↵Daniel Sanders2013-09-271-0/+7
| | | | | | | | intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
* [mips][msa] Tidy upDaniel Sanders2013-09-271-131/+119
| | | | | | | | | | | | lowerMSABinaryIntr, lowerMSABinaryImmIntr, lowerMSABranchIntr, and lowerMSAUnaryIntr were trivially small functions. Inlined them into their callers. lowerMSASplat now takes its callers SDLoc instead of making a new one. No functional change. llvm-svn: 191503
* [mips][msa] Expand all truncstores and loadexts for MSA as well as DSPDaniel Sanders2013-09-271-14/+16
| | | | llvm-svn: 191496
* [mips][msa] Added missing check in performSRACombineDaniel Sanders2013-09-271-0/+4
| | | | | | | | | | Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D1755 llvm-svn: 191495
* [mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. ↵Daniel Sanders2013-09-241-0/+70
| | | | | | not intrinsics) llvm-svn: 191306
* [mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal ↵Daniel Sanders2013-09-241-0/+157
| | | | | | IR (i.e. not intrinsics) llvm-svn: 191304
* [mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-241-0/+74
| | | | llvm-svn: 191302
* [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-241-0/+78
| | | | llvm-svn: 191301
* [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching ↵Daniel Sanders2013-09-241-61/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
* [mips][msa] Non-constant BUILD_VECTOR's should be expanded to ↵Daniel Sanders2013-09-241-0/+17
| | | | | | | | INSERT_VECTOR_ELT instead of memory operations. The resulting code is the same length, but doesnt cause memory traffic or latency. llvm-svn: 191297
* [mips][msa] Added partial support for matching fmax_a from normal IR (i.e. ↵Daniel Sanders2013-09-241-0/+1
| | | | | | | | not intrinsics) This covers the case where fmax_a can be used to implement ISD::FABS. llvm-svn: 191296
* [mips][msa] Added support for matching andi, ori, nori, and xori from normal ↵Daniel Sanders2013-09-241-0/+14
| | | | | | IR (i.e. not intrinsics) llvm-svn: 191293
* [mips][msa] Added support for matching max, maxi, min, mini from normal IR ↵Daniel Sanders2013-09-241-8/+92
| | | | | | (i.e. not intrinsics) llvm-svn: 191291
* [mips][msa] Added support for matching bsel and bseli from normal IR (i.e. ↵Daniel Sanders2013-09-241-0/+11
| | | | | | | | not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. llvm-svn: 191290
* [mips][msa] Added support for matching comparisons from normal IR (i.e. not ↵Daniel Sanders2013-09-241-0/+116
| | | | | | | | | intrinsics) MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. llvm-svn: 191286
* [mips][msa] Added support for matching slli, srai, and srli from normal IR ↵Daniel Sanders2013-09-241-0/+18
| | | | | | (i.e. not intrinsics) llvm-svn: 191285
* [mips][msa] Added support for matching addvi, and subvi from normal IR (i.e. ↵Daniel Sanders2013-09-231-0/+30
| | | | | | not intrinsics) llvm-svn: 191203
* [mips][msa] Added support for matching insert and copy from normal IR (i.e. ↵Daniel Sanders2013-09-231-0/+158
| | | | | | | | | | | not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
* [mips][msa] Added support for matching pcnt from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-231-0/+6
| | | | llvm-svn: 191198
* [mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-231-2/+48
| | | | llvm-svn: 191195
* [mips][msa] Added support for matching and, or, and xor from normal IR (i.e. ↵Daniel Sanders2013-09-231-0/+9
| | | | | | not intrinsics) llvm-svn: 191194
* Partially revert r191192: Fix -Wunused-variable error when assertions are ↵Daniel Sanders2013-09-231-9/+0
| | | | | | | | | disabled and -Werror is in use. An unrelated change crept in because 'svn revert' isn't recursive by default. The unrelated changes have been reverted. llvm-svn: 191193
* Fix -Wunused-variable error when assertions are disabled and -Werror is in use.Daniel Sanders2013-09-231-3/+9
| | | | llvm-svn: 191192
* [mips][msa] Implemented build_vector using ldi, fill, and custom ↵Daniel Sanders2013-09-231-0/+109
| | | | | | | | | | | | | | | | | | SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal llvm-svn: 191191
* [mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv ↵Daniel Sanders2013-09-111-0/+36
| | | | | | from normal IR (i.e. not intrinsics) llvm-svn: 190518
* [mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, ↵Daniel Sanders2013-09-111-0/+41
| | | | | | fsqrt, and fsub from normal IR (i.e. not intrinsics) llvm-svn: 190512
* [mips][msa] Added support for matching div_[su] from normal IR (i.e. not ↵Daniel Sanders2013-09-111-0/+12
| | | | | | intrinsics) llvm-svn: 190509
OpenPOWER on IntegriCloud