diff options
| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-11 10:38:58 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-11 10:38:58 +0000 |
| commit | 607952bdadd541007954f449de76aeaa824ce3c7 (patch) | |
| tree | c423d88335423b87d463599376fba9d7d4029325 /llvm/lib/Target/Mips/MipsSEISelLowering.cpp | |
| parent | c531daefd9cc627c8c348eee1547273660a1e3c5 (diff) | |
| download | bcm5719-llvm-607952bdadd541007954f449de76aeaa824ce3c7.tar.gz bcm5719-llvm-607952bdadd541007954f449de76aeaa824ce3c7.zip | |
[mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics)
llvm-svn: 190509
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSEISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSEISelLowering.cpp | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp index 0a39dda426d..2de21eaffbe 100644 --- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp @@ -160,6 +160,8 @@ addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { setOperationAction(ISD::STORE, Ty, Legal); setOperationAction(ISD::ADD, Ty, Legal); + setOperationAction(ISD::SDIV, Ty, Legal); + setOperationAction(ISD::UDIV, Ty, Legal); } void MipsSETargetLowering:: @@ -877,6 +879,16 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO); case Intrinsic::mips_bz_v: return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO); + case Intrinsic::mips_div_s_b: + case Intrinsic::mips_div_s_h: + case Intrinsic::mips_div_s_w: + case Intrinsic::mips_div_s_d: + return lowerMSABinaryIntr(Op, DAG, ISD::SDIV); + case Intrinsic::mips_div_u_b: + case Intrinsic::mips_div_u_h: + case Intrinsic::mips_div_u_w: + case Intrinsic::mips_div_u_d: + return lowerMSABinaryIntr(Op, DAG, ISD::UDIV); } } |
