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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-23 12:57:42 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-23 12:57:42 +0000 |
| commit | 8ca81e484ea2b28abc4e857926ae67bc27d5334f (patch) | |
| tree | 87f27e815dc0abb9bd068836267265182c035fa7 /llvm/lib/Target/Mips/MipsSEISelLowering.cpp | |
| parent | 5f38701d5a7316bcb0abc043ac60ba16dcb8d438 (diff) | |
| download | bcm5719-llvm-8ca81e484ea2b28abc4e857926ae67bc27d5334f.tar.gz bcm5719-llvm-8ca81e484ea2b28abc4e857926ae67bc27d5334f.zip | |
[mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics)
llvm-svn: 191194
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSEISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSEISelLowering.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp index 41bf01744b5..9532c9d7275 100644 --- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp @@ -162,14 +162,17 @@ addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); setOperationAction(ISD::ADD, Ty, Legal); + setOperationAction(ISD::AND, Ty, Legal); setOperationAction(ISD::CTLZ, Ty, Legal); setOperationAction(ISD::MUL, Ty, Legal); + setOperationAction(ISD::OR, Ty, Legal); setOperationAction(ISD::SDIV, Ty, Legal); setOperationAction(ISD::SHL, Ty, Legal); setOperationAction(ISD::SRA, Ty, Legal); setOperationAction(ISD::SRL, Ty, Legal); setOperationAction(ISD::SUB, Ty, Legal); setOperationAction(ISD::UDIV, Ty, Legal); + setOperationAction(ISD::XOR, Ty, Legal); } // Enable MSA support for the given floating-point type and Register class. @@ -895,6 +898,8 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_addv_w: case Intrinsic::mips_addv_d: return lowerMSABinaryIntr(Op, DAG, ISD::ADD); + case Intrinsic::mips_and_v: + return lowerMSABinaryIntr(Op, DAG, ISD::AND); case Intrinsic::mips_bnz_b: case Intrinsic::mips_bnz_h: case Intrinsic::mips_bnz_w: @@ -959,6 +964,8 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_nlzc_w: case Intrinsic::mips_nlzc_d: return lowerMSAUnaryIntr(Op, DAG, ISD::CTLZ); + case Intrinsic::mips_or_v: + return lowerMSABinaryIntr(Op, DAG, ISD::OR); case Intrinsic::mips_sll_b: case Intrinsic::mips_sll_h: case Intrinsic::mips_sll_w: @@ -979,6 +986,8 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_subv_w: case Intrinsic::mips_subv_d: return lowerMSABinaryIntr(Op, DAG, ISD::SUB); + case Intrinsic::mips_xor_v: + return lowerMSABinaryIntr(Op, DAG, ISD::XOR); } } |
