summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* [mips] Delete register class HWRegs64.Akira Hatanaka2013-08-081-1/+0
| | | | | | No functionality change. llvm-svn: 188016
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-061-8/+8
| | | | llvm-svn: 187832
* Clean up code for Mips16 large frame handling.Reed Kotler2013-08-041-0/+2
| | | | llvm-svn: 187701
* Checkin in of first of several patches to finish implementation ofReed Kotler2013-05-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
* [mips] Split the DSP control register and define one register for each field ofAkira Hatanaka2013-05-031-1/+5
| | | | | | | | | | | its fields. This removes false dependencies between DSP instructions which access different fields of the the control register. Implicit register operands are added to instructions RDDSP and WRDSP after instruction selection, depending on the value of the mask operand. llvm-svn: 181041
* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-311-10/+3
| | | | | | | Each target implementation was needlessly recomputing the index. Part of rdar://13076458 llvm-svn: 174083
* [mips] Implement MipsRegisterInfo::getRegPressureLimit.Akira Hatanaka2013-01-221-0/+22
| | | | llvm-svn: 173197
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-2/+2
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-12/+12
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* [mips] Stop reserving register AT and use register scavenger when a scratchAkira Hatanaka2012-11-031-2/+2
| | | | | | register is needed. llvm-svn: 167341
* [mips] Do not reserve all 64-bit registers, but only the ones which need to beAkira Hatanaka2012-11-021-8/+4
| | | | | | | reserved. Without this fix, RegScavenger::getRegsAvailable incorrectly returns an empty set of integer registers. llvm-svn: 167335
* This patch is for the implementation of mips16 complex pattern addr16.Reed Kotler2012-10-281-5/+12
| | | | | | | | | | | | | | | | | | | | | Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. llvm-svn: 166897
* Add MIPS accumulator and DSP control registers.Akira Hatanaka2012-09-211-0/+3
| | | | llvm-svn: 164429
* Add a member of type Mips16InstrInfo/MipsSEInstrInfo to classAkira Hatanaka2012-08-221-3/+2
| | | | | | | | Mips16RegisterInfo/MipsSERegisterInfo. No changes in functionality. llvm-svn: 162413
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-221-2/+1
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
* Add register Mips::GP to the list of reserved registers if target is bare-metalAkira Hatanaka2012-08-221-0/+6
| | | | | | | | to prevent it from being clobbered. mips uses $gp to access small data section. This bug was originally reported by Carl Norum. llvm-svn: 162340
* Implement MipsSERegisterInfo::eliminateCallFramePseudoInstr. The function emitsAkira Hatanaka2012-07-311-9/+0
| | | | | | | instructions that decrement and increment the stack pointer before and after a call when the function does not have a reserved call frame. llvm-svn: 161093
* Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo andAkira Hatanaka2012-07-311-63/+1
| | | | | | MipsSERegisterInfo. llvm-svn: 161092
* Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering.Akira Hatanaka2012-07-311-2/+2
| | | | | | | The frame object which points to the dynamically allocated area will not be needed after changes are made to cease reserving call frames. llvm-svn: 161076
* Eliminate the stack slot used to save the global base register.Akira Hatanaka2012-07-251-2/+1
| | | | | | | | The long branch pass (fixed in r160601) no longer uses the global base register to compute addresses of branch destinations, so it is not necessary to reserve a slot on the stack. llvm-svn: 160703
* Make register Mips::RA allocatable if not in mips16 mode.Akira Hatanaka2012-07-101-4/+8
| | | | llvm-svn: 159971
* Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling2012-06-281-1/+1
| | | | | | | | | include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. llvm-svn: 159312
* Fix coding style violations. Remove white spaces and tabs.Akira Hatanaka2012-06-141-6/+4
| | | | llvm-svn: 158471
* In MipsRegisterInfo::eliminateFrameIndex, call Mips::loadImmediateAkira Hatanaka2012-06-141-25/+7
| | | | | | to load an immediate that does not fit into 16-bit. llvm-svn: 158431
* Stop reserving register $gp. Do not call isGPFI to check whether a frame objectAkira Hatanaka2012-05-121-8/+1
| | | | | | is the $gp save slot. llvm-svn: 156694
* Fix a misleading comment.Akira Hatanaka2012-05-111-1/+1
| | | | llvm-svn: 156603
* Make register FP allocatable if the compiled function does not have dynamicAkira Hatanaka2012-05-091-2/+8
| | | | | | allocas. llvm-svn: 156458
* This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd2012-04-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. llvm-svn: 155395
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-9/+8
| | | | | | since they are equivalent. llvm-svn: 155188
* Turn on post register allocation scheduler.Akira Hatanaka2012-03-281-0/+5
| | | | llvm-svn: 153554
* Emit all directives except for ".cprestore" during asm printing rather than emitAkira Hatanaka2012-03-281-3/+1
| | | | | | | | | | | | | | | | them as machine instructions. Directives ".set noat" and ".set at" are now emitted only at the beginning and end of a function except in the case where they are emitted to enclose .cpload with an immediate operand that doesn't fit in 16-bit field or unaligned load/stores. Also, make the following changes: - Remove function isUnalignedLoadStore and use a switch-case statement to determine whether an instruction is an unaligned load or store. - Define helper function CreateMCInst which generates an instance of an MCInst from an opcode and a list of operands. llvm-svn: 153552
* Remove trailing white space.Akira Hatanaka2012-03-271-1/+1
| | | | llvm-svn: 153536
* Reserve hardware registers.Akira Hatanaka2012-03-271-0/+4
| | | | llvm-svn: 153486
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-1/+1
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Use uint16_t to store registers and opcode in static tables in the target ↵Craig Topper2012-03-111-2/+2
| | | | | | specific backends. llvm-svn: 152537
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-1/+1
| | | | | | size of static data. llvm-svn: 151996
* Changes for migrating to using register mask operands.Akira Hatanaka2012-03-011-33/+17
| | | | llvm-svn: 151847
* remove blanks, and some code formatJia Liu2012-02-281-12/+12
| | | | llvm-svn: 151625
* Add an option to use a virtual register as the global base register instead ofAkira Hatanaka2012-02-241-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
* remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.Jia Liu2012-02-171-1/+1
| | | | llvm-svn: 150805
* Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate toAkira Hatanaka2012-01-251-12/+34
| | | | | | | | expand offsets that do not fit in the 16-bit immediate field of load and store instructions. Also change the types of variables so that they are sufficiently large to handle 64-bit pointers. llvm-svn: 148916
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-2/+0
| | | | llvm-svn: 148578
* Cleanup Mips code and rename some variables. Patch by Jack CarterBruno Cardoso Lopes2011-12-301-92/+0
| | | | llvm-svn: 147383
* Add register HWR29 numbering. Patch by Jack CarterBruno Cardoso Lopes2011-12-061-0/+1
| | | | llvm-svn: 145910
* Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bitAkira Hatanaka2011-11-151-2/+4
| | | | | | registers and instructions when ABI is N64. llvm-svn: 144666
* Use array_lengthof to compute the number of iterations of a loop.Akira Hatanaka2011-11-071-6/+6
| | | | llvm-svn: 143991
* Fix function MipsRegisterInfo::getRegisterNumbering.Akira Hatanaka2011-09-271-33/+81
| | | | | | Return numbers of 64-bit registers. llvm-svn: 140609
* Add definitions of 64-bit register files. Add code for returning Mips64's ↵Akira Hatanaka2011-09-231-9/+56
| | | | | | | | sets of callee-saved registers and reserved registers. llvm-svn: 140395
* Add F31 to the set of callee-saved registers.Akira Hatanaka2011-09-221-1/+1
| | | | llvm-svn: 140315
* Make F31 and D15 non-reserved registers.Akira Hatanaka2011-09-091-2/+0
| | | | llvm-svn: 139420
OpenPOWER on IntegriCloud