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authorAkira Hatanaka <ahatanaka@mips.com>2012-03-28 00:24:17 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2012-03-28 00:24:17 +0000
commit047473e293d926a4a87aa7cfbb670d828c70c5e6 (patch)
tree534c82b7aba4786116dc6eccd3eacf9c6d3a9f1a /llvm/lib/Target/Mips/MipsRegisterInfo.cpp
parent5ba593f50942273c77b40e754172be7e3e434705 (diff)
downloadbcm5719-llvm-047473e293d926a4a87aa7cfbb670d828c70c5e6.tar.gz
bcm5719-llvm-047473e293d926a4a87aa7cfbb670d828c70c5e6.zip
Turn on post register allocation scheduler.
llvm-svn: 153554
Diffstat (limited to 'llvm/lib/Target/Mips/MipsRegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/Mips/MipsRegisterInfo.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
index f1af7067708..f30de449f6d 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -132,6 +132,11 @@ getReservedRegs(const MachineFunction &MF) const {
return Reserved;
}
+bool
+MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
+ return true;
+}
+
// This function eliminate ADJCALLSTACKDOWN,
// ADJCALLSTACKUP pseudo instructions
void MipsRegisterInfo::
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