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authorAkira Hatanaka <ahatanaka@mips.com>2011-11-15 18:53:55 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2011-11-15 18:53:55 +0000
commit6ee8fc88c7f92bdefe3b164a0de73479c080a412 (patch)
tree90409b65645ae200f9ad141462dc6bcfd2f6b7dc /llvm/lib/Target/Mips/MipsRegisterInfo.cpp
parent494913270ebac526ff40379aa50e6417e521d03b (diff)
downloadbcm5719-llvm-6ee8fc88c7f92bdefe3b164a0de73479c080a412.tar.gz
bcm5719-llvm-6ee8fc88c7f92bdefe3b164a0de73479c080a412.zip
Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bit
registers and instructions when ABI is N64. llvm-svn: 144666
Diffstat (limited to 'llvm/lib/Target/Mips/MipsRegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/Mips/MipsRegisterInfo.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
index 5331f09efd5..06c4a6641c5 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -285,7 +285,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
(FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
- FrameReg = Mips::SP;
+ FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
else
FrameReg = getFrameRegister(MF);
@@ -334,8 +334,10 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
unsigned MipsRegisterInfo::
getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
+ bool IsN64 = Subtarget.isABI_N64();
- return TFI->hasFP(MF) ? Mips::FP : Mips::SP;
+ return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
+ (IsN64 ? Mips::SP_64 : Mips::SP);
}
unsigned MipsRegisterInfo::
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