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* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [mips] Correct predicates for MSA pseudo instructionsSimon Dardis2018-06-141-1/+2
| | | | llvm-svn: 334708
* [mips] Sink PredicateControl further down the class hierarchy.Simon Dardis2018-05-301-1/+1
| | | | | | | | | | | | | | | | Previously PredicateControl in some cases was a member of <X>Inst classes for some X (DSP, EVA) or was in more irregular place in the hierarchry for any given instruction. This patch moves PredicateControl down to the root so that it is consistently available. Then correct the base class of microMIPS instructions as using EncodingPredicates instead of the general Predicates field of Instruction. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D47526 llvm-svn: 333536
* [mips] Use PredicateControl for the MSA ASE instructions. NFC.Daniel Sanders2015-09-241-17/+7
| | | | | | | | | | Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13092 llvm-svn: 248486
* Make it possible for the Subtarget to change between functionEric Christopher2014-07-101-1/+1
| | | | | | | | passes in the mips back end. This, unfortunately, required a bit of churn in the various predicates to use a pointer rather than a reference. llvm-svn: 212744
* [mips][msa] Add DLSA instruction.Matheus Almeida2014-02-101-0/+18
| | | | llvm-svn: 201081
* [mips][msa] Add insert.d instruction.Matheus Almeida2014-01-311-0/+13
| | | | | | This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200543
* [mips][msa] Add fill.d instruction.Matheus Almeida2014-01-291-0/+11
| | | | | | | This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200400
* [mips][msa] Add copy_{u,s}.d.Matheus Almeida2014-01-291-0/+17
| | | | | | | These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
* [mips][msa] Pseudo instructions require HasMSA too. Inherit from MSAPseudo ↵Daniel Sanders2013-11-201-1/+1
| | | | | | | | | | | instead of MipsPseudo There's no test case for this commit. This is because it is doubtful that the incorrect behaviour can actually trigger. When MSA is not enabled, the type legalizer should have eliminated all occurrences of patterns the affected pseudo-instruction could possibly match before instruction selection occurs. llvm-svn: 195252
* [mips][msa] Direct Object Emission support for the LSA instruction.Matheus Almeida2013-10-231-3/+15
| | | | llvm-svn: 193240
* [mips][msa] Direct Object Emission support for conditional branches.Matheus Almeida2013-10-221-2/+20
| | | | | | | | | | | | These branches have a 16-bit offset (R_MIPS_PC16). List of conditional branch instructions: bnz.{b,h,w,d} bnz.v bz.{b,h,w,d} bz.v llvm-svn: 193157
* [mips][msa] Direct Object Emission support for LD/ST instructions.Matheus Almeida2013-10-211-0/+11
| | | | llvm-svn: 193082
* [mips][msa] Direct Object Emission support for LDI instructions.Matheus Almeida2013-10-211-0/+5
| | | | llvm-svn: 193081
* [mips][msa] Direct Object Emission support for MOVE.v.Matheus Almeida2013-10-211-0/+5
| | | | llvm-svn: 193080
* [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. Matheus Almeida2013-10-211-0/+20
| | | | | | | | These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
* [mips][msa] Fix definition of SLD instruction.Matheus Almeida2013-10-211-0/+13
| | | | | | | The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. llvm-svn: 193076
* [mips][msa] Added lsa instructionDaniel Sanders2013-10-171-0/+6
| | | | llvm-svn: 192895
* [mips][msa] Direct Object Emission support for BIT instructions.Matheus Almeida2013-10-141-0/+28
| | | | | | | | | | | | | | | | | | List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
* [mips][msa] Direct Object Emission support for VEC instructions.Matheus Almeida2013-10-141-0/+7
| | | | | | | List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
* [mips][msa] Direct Object Emission for the majority of the ELM instructions.Matheus Almeida2013-10-141-0/+67
| | | | | | | | | | List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
* [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.Matheus Almeida2013-10-141-0/+39
| | | | | | | | | INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192582
* This reverts 192447 because of compiler warning generated on darwin build.Matheus Almeida2013-10-111-39/+0
| | | | llvm-svn: 192451
* This reverts r192449 because of compiler warning generated on darwin build.Matheus Almeida2013-10-111-67/+0
| | | | llvm-svn: 192450
* [mips][msa] Direct Object Emission for the majority of the ELM instructions.Matheus Almeida2013-10-111-0/+67
| | | | llvm-svn: 192449
* [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.Matheus Almeida2013-10-111-0/+39
| | | | | | | | INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192447
* [mips][msa] Direct Object Emission for I8 instructions.Jack Carter2013-09-301-0/+7
| | | | | | | | | This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
* [mips][msa] Direct Object Emission for I5 instructions.Jack Carter2013-09-301-0/+7
| | | | | | | | | This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
* [mips][msa] Direct Object Emission for 2R instructions.Jack Carter2013-09-301-0/+5
| | | | | | | | | This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}. Patch by Matheus Almeida llvm-svn: 191685
* [PATCH 1/4] [mips][msa] Source register of FILL instructions is GPRJack Carter2013-09-301-0/+11
| | | | | | | | and not an MSA register Patch by Matheus Almeida llvm-svn: 191684
* [mips][msa] Direct Object Emission for 3RF instructions.Jack Carter2013-09-261-0/+7
| | | | | | Patch by Matheus Almeida llvm-svn: 191461
* [mips][msa] Direct Object Emission for 3R instructions.Jack Carter2013-09-261-0/+7
| | | | | | | | This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
* [mips][msa] Direct Object Emission support for the MSA instruction set. Jack Carter2013-09-251-0/+5
| | | | | | | | | | In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
* [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.vDaniel Sanders2013-08-281-0/+5
| | | | | | | | | | | | | These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
* [mips][msa] Added cfcmsa, and ctcmsaDaniel Sanders2013-08-281-0/+5
| | | | | | | | The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. llvm-svn: 189468
* [mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.vDaniel Sanders2013-08-201-0/+5
| | | | llvm-svn: 188767
* [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)Jack Carter2013-08-151-0/+77
| | | | | | | | | | | | | Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
* [Mips][msa] Added initial MSA support.Jack Carter2013-08-131-0/+34
* msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
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