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| author | Matheus Almeida <matheus.almeida@imgtec.com> | 2014-02-10 12:05:17 +0000 |
|---|---|---|
| committer | Matheus Almeida <matheus.almeida@imgtec.com> | 2014-02-10 12:05:17 +0000 |
| commit | 4b27eb588cd95d953110e1eb009f5e5018a9955c (patch) | |
| tree | db4c8c0dd684bf696c8354c559691c13cbc28e50 /llvm/lib/Target/Mips/MipsMSAInstrFormats.td | |
| parent | b4133b25e7641bd9d76bba8ee3b960e13d64ea66 (diff) | |
| download | bcm5719-llvm-4b27eb588cd95d953110e1eb009f5e5018a9955c.tar.gz bcm5719-llvm-4b27eb588cd95d953110e1eb009f5e5018a9955c.zip | |
[mips][msa] Add DLSA instruction.
llvm-svn: 201081
Diffstat (limited to 'llvm/lib/Target/Mips/MipsMSAInstrFormats.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsMSAInstrFormats.td | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsMSAInstrFormats.td b/llvm/lib/Target/Mips/MipsMSAInstrFormats.td index 3942d05914f..6bd0366b52e 100644 --- a/llvm/lib/Target/Mips/MipsMSAInstrFormats.td +++ b/llvm/lib/Target/Mips/MipsMSAInstrFormats.td @@ -27,6 +27,10 @@ class MSASpecial : MSAInst { let Inst{31-26} = 0b000000; } +class MSA64Special : MSA64Inst { + let Inst{31-26} = 0b000000; +} + class MSAPseudo<dag outs, dag ins, list<dag> pattern, InstrItinClass itin = IIPseudo>: MipsPseudo<outs, ins, pattern, itin> { @@ -445,3 +449,17 @@ class SPECIAL_LSA_FMT<bits<6> minor>: MSASpecial { let Inst{7-6} = sa; let Inst{5-0} = minor; } + +class SPECIAL_DLSA_FMT<bits<6> minor>: MSA64Special { + bits<5> rs; + bits<5> rt; + bits<5> rd; + bits<2> sa; + + let Inst{25-21} = rs; + let Inst{20-16} = rt; + let Inst{15-11} = rd; + let Inst{10-8} = 0b000; + let Inst{7-6} = sa; + let Inst{5-0} = minor; +} |
