summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Mips/MipsMSAInstrFormats.td
diff options
context:
space:
mode:
authorMatheus Almeida <matheus.almeida@imgtec.com>2014-01-29 15:12:02 +0000
committerMatheus Almeida <matheus.almeida@imgtec.com>2014-01-29 15:12:02 +0000
commitec079d9e1d5bdc5372065b51dcb202c7d6bf682c (patch)
treebdc7924a4fd8e11a7bb1539e351637618d646793 /llvm/lib/Target/Mips/MipsMSAInstrFormats.td
parent4cb577c614f144d25895c3bbb46d8b4f5590db17 (diff)
downloadbcm5719-llvm-ec079d9e1d5bdc5372065b51dcb202c7d6bf682c.tar.gz
bcm5719-llvm-ec079d9e1d5bdc5372065b51dcb202c7d6bf682c.zip
[mips][msa] Add fill.d instruction.
This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200400
Diffstat (limited to 'llvm/lib/Target/Mips/MipsMSAInstrFormats.td')
-rw-r--r--llvm/lib/Target/Mips/MipsMSAInstrFormats.td11
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsMSAInstrFormats.td b/llvm/lib/Target/Mips/MipsMSAInstrFormats.td
index d463d60354c..937898f9d55 100644
--- a/llvm/lib/Target/Mips/MipsMSAInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsMSAInstrFormats.td
@@ -96,6 +96,17 @@ class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
let Inst{5-0} = minor;
}
+class MSA_2R_FILL_D_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSA64Inst {
+ bits<5> rs;
+ bits<5> wd;
+
+ let Inst{25-18} = major;
+ let Inst{17-16} = df;
+ let Inst{15-11} = rs;
+ let Inst{10-6} = wd;
+ let Inst{5-0} = minor;
+}
+
class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
bits<5> ws;
bits<5> wd;
OpenPOWER on IntegriCloud