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* [MIPS GlobalISel] Select phi instruction for integers Petar Avramovic2019-02-141-0/+4
| | | | | | | | Select G_PHI for integers for MIPS32. Differential Revision: https://reviews.llvm.org/D58183 llvm-svn: 354025
* [MIPS GlobalISel] Select branch instructionsPetar Avramovic2019-02-141-0/+4
| | | | | | | | | | | | | Select G_BR and G_BRCOND for MIPS32. Unconditional branch G_BR does not have register operand, for that reason we only add tests. Since conditional branch G_BRCOND compares register to zero on MIPS32, explicit extension must be performed on i1 condition in order to set high bits to appropriate value. Differential Revision: https://reviews.llvm.org/D58182 llvm-svn: 354022
* [MIPS GlobalISel] Select any extending load and truncating storePetar Avramovic2019-02-081-1/+5
| | | | | | | | | | | | | | | | | | Make behavior of G_LOAD in widenScalar same as for G_ZEXTLOAD and G_SEXTLOAD. That is perform widenScalarDst to size given by the target and avoid additional checks in common code. Targets can reorder or add additional rules in LegalizeRuleSet for the opcode to achieve desired behavior. Select extending load that does not have specified type of extension into zero extending load. Select truncating store that stores number of bytes indicated by size in MachineMemoperand. Differential Revision: https://reviews.llvm.org/D57454 llvm-svn: 353520
* [MIPS GlobalISel] Select mulPetar Avramovic2019-02-081-0/+4
| | | | | | | | Legalize and select G_MUL for s32 and smaller types for MIPS32. Differential Revision: https://reviews.llvm.org/D57816 llvm-svn: 353506
* [MIPS GlobalISel] Select subPetar Avramovic2019-01-281-2/+2
| | | | | | | | | Lower G_USUBO and G_USUBE. Add narrowScalar for G_SUB. Legalize and select G_SUB for MIPS 32. Differential Revision: https://reviews.llvm.org/D53416 llvm-svn: 352351
* [MIPS GlobalISel] Select zero extending and sign extending loadPetar Avramovic2019-01-241-0/+5
| | | | | | | | | Select zero extending and sign extending load for MIPS32. Use size from MachineMemOperand to determine number of bytes to load. Differential Revision: https://reviews.llvm.org/D57099 llvm-svn: 352038
* GlobalISel: Allow shift amount to be a different typeMatt Arsenault2019-01-221-3/+4
| | | | | | | | | For AMDGPU the shift amount is never 64-bit, and this needs to use a 32-bit shift. X86 uses i8, but seemed to be hacking around this before. llvm-svn: 351882
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [MIPS GlobalISel] Select G_SELECTPetar Avramovic2018-12-251-0/+5
| | | | | | | | | | Add widen scalar for type index 1 (i1 condition) for G_SELECT. Select G_SELECT for pointer, s32(integer) and smaller low level types on MIPS32. Differential Revision: https://reviews.llvm.org/D56001 llvm-svn: 350063
* [MIPS GlobalISel] Select G_SDIV, G_UDIV, G_SREM and G_UREMPetar Avramovic2018-12-181-0/+6
| | | | | | | | | | | | Add support for s64 libcalls for G_SDIV, G_UDIV, G_SREM and G_UREM and use integer type of correct size when creating arguments for CLI.lowerCall. Select G_SDIV, G_UDIV, G_SREM and G_UREM for types s8, s16, s32 and s64 on MIPS32. Differential Revision: https://reviews.llvm.org/D55651 llvm-svn: 349499
* [MIPS GlobalISel] ClampScalar G_AND G_OR and G_XORPetar Avramovic2018-12-181-1/+5
| | | | | | | | | | Add narrowScalar for G_AND and G_XOR. Legalize G_AND G_OR and G_XOR for types other then s32 with clampScalar on MIPS32. Differential Revision: https://reviews.llvm.org/D55362 llvm-svn: 349475
* [MIPS GlobalISel] Remove switch statement (fix r349346 for MSVC)Petar Avramovic2018-12-171-6/+1
| | | | | | | Temporarily remove switch statement without any case labels in function legalizeCustom in order to fix r349346 for MSVC. llvm-svn: 349356
* [MIPS GlobalISel] Lower G_UADDE and narrowScalar G_ADDPetar Avramovic2018-12-171-30/+5
| | | | | | | | Lower G_UADDE and legalize G_ADD using narrowScalar on MIPS32. Differential Revision: https://reviews.llvm.org/D54580 llvm-svn: 349346
* [GISel]: Provide standard interface to observe changes in GISel passesAditya Nandakumar2018-12-051-1/+2
| | | | | | | | | | | | | https://reviews.llvm.org/D54980 This provides a standard API across GISel passes to observe and notify passes about changes (insertions/deletions/mutations) to MachineInstrs. This patch also removes the recordInsertion method in MachineIRBuilder and instead provides method to setObserver. Reviewed by: vkeles. llvm-svn: 348406
* [MIPS GlobalISel] narrowScalar G_CONSTANTPetar Avramovic2018-11-091-23/+1
| | | | | | | | Legalize s64 G_CONSTANT using narrowScalar on MIPS 32. Differential Revision: https://reviews.llvm.org/D54255 llvm-svn: 346495
* [MIPS GlobalISel] Set operand order for G_MERGE and G_UNMERGEPetar Avramovic2018-11-071-4/+4
| | | | | | | | | Set operands order for G_MERGE_VALUES and G_UNMERGE_VALUES so that least significant bits always go first, regardless of endianness. Differential Revision: https://reviews.llvm.org/D54098 llvm-svn: 346305
* [MIPS GlobalISel] Legalize constantsPetar Jovanovic2018-10-171-1/+24
| | | | | | | | | | Legalize s1, s8, s16 and s64 G_CONSTANT for MIPS32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D53077 llvm-svn: 344684
* [MIPS GlobalISel] Legalize i64 addPetar Jovanovic2018-10-081-1/+47
| | | | | | | | | | Custom legalize s64 G_ADD for MIPS32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D52652 llvm-svn: 344007
* [MIPS GlobalISel] Select icmpPetar Jovanovic2018-09-101-0/+4
| | | | | | | | | | Select 32bit integer compare instructions for MIPS32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D51489 llvm-svn: 341840
* [MIPS GlobalISel] Legalize i8 and i16 addPetar Jovanovic2018-08-261-1/+3
| | | | | | | | | | | | Legalize G_ADD for types smaller than i32. LegalizationArtifactCombiner replaces extend instructions with appropriate bitwise instructions. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D51213 llvm-svn: 340697
* [MIPS GlobalISel] Select bitwise instructionsPetar Jovanovic2018-08-211-0/+3
| | | | | | | | | | Select bitwise instructions for i32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D50183 llvm-svn: 340258
* [MIPS GlobalISel] Select global addressPetar Jovanovic2018-08-011-0/+3
| | | | | | | | | | Select G_GLOBAL_VALUE for position dependent code. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D49803 llvm-svn: 338499
* [MIPS GlobalISel] Lower pointer argumentsPetar Jovanovic2018-07-251-1/+1
| | | | | | | | | | | | Add support for lowering pointer arguments. Changing type from pointer to integer is already done in MipsTargetLowering::getRegisterTypeForCallingConv. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D49419 llvm-svn: 337912
* [MIPS GlobalISel] Select instructions to load and store i32 on stackPetar Jovanovic2018-07-161-0/+13
| | | | | | | | | | | Add code for selection of G_LOAD, G_STORE, G_GEP, G_FRAMEINDEX and G_CONSTANT. Support loads and stores of i32 values. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D48957 llvm-svn: 337168
* [GlobalISel][Mips] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) ↵Roman Tereshin2018-05-311-0/+2
| | | | | | | | | | | | call for Mips Reviewers: aemerson, qcolombet Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46339 llvm-svn: 333665
* [MIPS GlobalISel] remove superfluous #includes (NFC)Petar Jovanovic2018-04-121-4/+0
| | | | | | | Remove superfluous #includes. Minor code style change in MipsCallLowering::lowerFormalArguments(). llvm-svn: 329926
* [MIPS GlobalISel] Select add i32, i32Petar Jovanovic2018-04-111-0/+6
| | | | | | | | | | | | | Add the minimal support necessary to lower a function that returns the sum of two i32 values. Support argument/return lowering of i32 values through registers only. Add tablegen for regbankselect and instructionselect. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D44304 llvm-svn: 329819
* [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to ↵Craig Topper2018-03-291-1/+1
| | | | | | | | | | | | CodeGen layer. Currently EVT is in the IR layer only because of Function.cpp needing a very small piece of the functionality of EVT::getEVTString(). The rest of EVT is used in codegen making CodeGen a better place for it. The previous code converted a Type* to EVT and then called getEVTString. This was only expected to handle the primitive types from Type*. Since there only a few primitive types, we can just print them as strings directly. Differential Revision: https://reviews.llvm.org/D45017 llvm-svn: 328806
* Fix layering by moving ValueTypes.h from CodeGen to IRDavid Blaikie2018-03-231-1/+1
| | | | | | ValueTypes.h is implemented in IR already. llvm-svn: 328397
* [MIPS GlobalISel] Adding GlobalISelPetar Jovanovic2018-02-231-0/+24
Add GlobalISel infrastructure up to the point where we can select a ret void. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D43583 llvm-svn: 325888
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