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| author | Petar Avramovic <Petar.Avramovic@rt-rk.com> | 2019-02-14 11:39:53 +0000 |
|---|---|---|
| committer | Petar Avramovic <Petar.Avramovic@rt-rk.com> | 2019-02-14 11:39:53 +0000 |
| commit | 5d9b8eed85e5530ce961bbe94709d83d773e46dc (patch) | |
| tree | b32d138075a2a10da5ca7633117793547888d00a /llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | |
| parent | 24383cd7bbe2716a1805cdbab908ff592a811cd7 (diff) | |
| download | bcm5719-llvm-5d9b8eed85e5530ce961bbe94709d83d773e46dc.tar.gz bcm5719-llvm-5d9b8eed85e5530ce961bbe94709d83d773e46dc.zip | |
[MIPS GlobalISel] Select branch instructions
Select G_BR and G_BRCOND for MIPS32.
Unconditional branch G_BR does not have register operand,
for that reason we only add tests.
Since conditional branch G_BRCOND compares register to zero on MIPS32,
explicit extension must be performed on i1 condition in order to set
high bits to appropriate value.
Differential Revision: https://reviews.llvm.org/D58182
llvm-svn: 354022
Diffstat (limited to 'llvm/lib/Target/Mips/MipsLegalizerInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp index 2fe6c481091..c02fa95222c 100644 --- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp +++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -52,6 +52,10 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { .minScalar(0, s32) .minScalar(1, s32); + getActionDefinitionsBuilder(G_BRCOND) + .legalFor({s32}) + .minScalar(0, s32); + getActionDefinitionsBuilder({G_AND, G_OR, G_XOR}) .legalFor({s32}) .clampScalar(0, s32, s32); |
