| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [mips][microMIPS] Implement SLL and NOP instructions | Zoran Jovanovic | 2015-07-01 | 1 | -0/+2 |
| * | [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. | Daniel Sanders | 2015-06-27 | 1 | -10/+14 |
| * | [mips] [IAS] Add partial support for the ULW pseudo-instruction. | Toma Tabacu | 2015-06-26 | 1 | -0/+3 |
| * | [mips][microMIPS] Implement BREAK, EHB and EI instructions | Zoran Jovanovic | 2015-06-24 | 1 | -2/+8 |
| * | [mips] [IAS] Add partial support for the ULHU pseudo-instruction. | Toma Tabacu | 2015-06-23 | 1 | -0/+3 |
| * | [mips] [IAS] Add support for the B{L,G}{T,E}(U) branch pseudo-instructions. | Toma Tabacu | 2015-06-17 | 1 | -0/+14 |
| * | Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate operand.... | Toma Tabacu | 2015-06-11 | 1 | -0/+11 |
| * | [mips][microMIPS] Implement ERET and ERETNC instructions | Zoran Jovanovic | 2015-06-11 | 1 | -0/+2 |
| * | [mips] Change existing uimm10 operand to restrict the accepted immediates | Zoran Jovanovic | 2015-06-11 | 1 | -0/+8 |
| * | [mips][microMIPSr6] Implement SEB and SEH instructions | Zoran Jovanovic | 2015-05-27 | 1 | -2/+2 |
| * | [mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructions | Zoran Jovanovic | 2015-05-19 | 1 | -7/+7 |
| * | [mips][microMIPSr6] Implement AND and ANDI instructions | Zoran Jovanovic | 2015-05-19 | 1 | -3/+4 |
| * | [mips][microMIPSr6] Implement ADD, ADDU and ADDIU instructions | Zoran Jovanovic | 2015-04-29 | 1 | -4/+5 |
| * | [mips][microMIPSr6] Implement BALC and BC instructions | Jozef Kolek | 2015-04-20 | 1 | -0/+4 |
| * | [mips][microMIPSr6] Implement initial subtarget support | Jozef Kolek | 2015-04-20 | 1 | -0/+5 |
| * | [mips] [IAS] Add support for the BNEZL and BEQZL pseudo-instructions. | Toma Tabacu | 2015-04-08 | 1 | -0/+4 |
| * | [mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic. | Toma Tabacu | 2015-04-08 | 1 | -4/+2 |
| * | [mips] Add itineraries for ext and ins instructions. | Kai Nacke | 2015-03-18 | 1 | -2/+2 |
| * | [mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction. | Toma Tabacu | 2015-03-17 | 1 | -0/+2 |
| * | [mips][microMIPS] Make usage of NOT16 by code generator | Jozef Kolek | 2015-03-11 | 1 | -0/+2 |
| * | [mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator | Jozef Kolek | 2015-03-04 | 1 | -1/+2 |
| * | [mips] Rename the LA/LI/DLI TableGen definitions and classes. NFC. | Toma Tabacu | 2015-03-04 | 1 | -6/+7 |
| * | [mips] Reformat some TableGen definitions. NFC. | Toma Tabacu | 2015-02-24 | 1 | -1/+1 |
| * | Reversed revision 229706. The reason is regression, which is caused by the | Jozef Kolek | 2015-02-20 | 1 | -2/+1 |
| * | [mips][microMIPS] Make usage of AND16, OR16 and XOR16 by code generator | Jozef Kolek | 2015-02-19 | 1 | -0/+2 |
| * | [mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator | Jozef Kolek | 2015-02-18 | 1 | -1/+2 |
| * | [mips][microMIPS] Implement JALX instruction | Jozef Kolek | 2015-02-18 | 1 | -2/+2 |
| * | [mips][microMIPS] Implement CodeGen support for SW16 and LW16 instructions | Zoran Jovanovic | 2015-02-04 | 1 | -0/+8 |
| * | [mips] Manually replace JAL pseudo-instructions with their JALR equivalent, i... | Toma Tabacu | 2015-01-30 | 1 | -2/+5 |
| * | [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B | Jozef Kolek | 2015-01-21 | 1 | -0/+2 |
| * | Reverted revision 226577. | Jozef Kolek | 2015-01-20 | 1 | -2/+0 |
| * | [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B | Jozef Kolek | 2015-01-20 | 1 | -0/+2 |
| * | Remove unused predicate. | Eric Christopher | 2015-01-14 | 1 | -2/+0 |
| * | [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions | Jozef Kolek | 2014-12-23 | 1 | -7/+8 |
| * | [mips] Support SELECT nodes for targets that don't have conditional-move inst... | Vasileios Kalintiris | 2014-12-12 | 1 | -0/+5 |
| * | [mips][microMIPS] Implement CodeGen support for LI16 instruction. | Jozef Kolek | 2014-12-11 | 1 | -0/+2 |
| * | [mips] Add synci instruction. | Daniel Sanders | 2014-11-27 | 1 | -1/+22 |
| * | Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. | Craig Topper | 2014-11-26 | 1 | -6/+6 |
| * | [mips][microMIPS] Implement CodeGen support for ADDIUS5 instruction. | Jozef Kolek | 2014-11-19 | 1 | -2/+3 |
| * | [mips][microMIPS] Implement SDBBP and RDHWR instructions. | Jozef Kolek | 2014-11-19 | 1 | -3/+3 |
| * | [mips] Add preliminary support for the MIPS II target. | Vasileios Kalintiris | 2014-11-11 | 1 | -0/+6 |
| * | ps][microMIPS] Implement CodeGen support for ANDI16 instruction | Zoran Jovanovic | 2014-11-05 | 1 | -2/+3 |
| * | ps][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions | Zoran Jovanovic | 2014-11-05 | 1 | -0/+2 |
| * | Reverted revisions 221351, 221352 and 221353. | Zoran Jovanovic | 2014-11-05 | 1 | -5/+2 |
| * | [mips][microMIPS] Implement CodeGen support for ANDI16 instruction | Zoran Jovanovic | 2014-11-05 | 1 | -2/+3 |
| * | [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions | Zoran Jovanovic | 2014-11-05 | 1 | -0/+2 |
| * | [mips] Move COP2 & COP3 load/store instructions from MipsInstrFPU.td to MipsI... | Vasileios Kalintiris | 2014-11-04 | 1 | -0/+54 |
| * | [mips] Add support for COP0's Branch-On-Cond-Likely instructions | Vasileios Kalintiris | 2014-10-17 | 1 | -6/+25 |
| * | [mips] Marked the DI/EI instruction aliases as MIPS32r2 | Vasileios Kalintiris | 2014-10-16 | 1 | -2/+2 |
| * | [mips] Fix disassembly of [ls][wd]c[23], cache, and pref ... | Daniel Sanders | 2014-10-01 | 1 | -4/+6 |
