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| author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-11-05 15:46:53 +0000 |
|---|---|---|
| committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-11-05 15:46:53 +0000 |
| commit | f4f5f1e272a33a34cb5b7e00a10f2399d1c75f17 (patch) | |
| tree | 225eafe2b42e42f664017ec4ed129de376a866c7 /llvm/lib/Target/Mips/MipsInstrInfo.td | |
| parent | e548bb06349aedc248aae9a8785fa0963cc9ace0 (diff) | |
| download | bcm5719-llvm-f4f5f1e272a33a34cb5b7e00a10f2399d1c75f17.tar.gz bcm5719-llvm-f4f5f1e272a33a34cb5b7e00a10f2399d1c75f17.zip | |
[mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions
Differential Revision: http://reviews.llvm.org/D5933
llvm-svn: 221352
Diffstat (limited to 'llvm/lib/Target/Mips/MipsInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 2962972726e..2562034852b 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1137,10 +1137,12 @@ def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; /// Shift Instructions +let AdditionalPredicates = [NotInMicroMips] in { def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl, immZExt5>, SRA_FM<0, 0>; def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl, immZExt5>, SRA_FM<2, 0>; +} def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra, immZExt5>, SRA_FM<3, 0>; def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>, |
