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* [mips] Correct c.cond.fmt instruction definition.Simon Dardis2017-01-161-2/+6
| | | | | | | | | | | | | | | Permit explicit $fcc<X> operand in c.cond.fmt instruction. Add c.cond.fmt to the MIPS to microMIPS instruction mapping table. Check that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for c.cond.fmt, bc1t, bc1f. Reviewers: seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D24510 llvm-svn: 292117
* Revert "[mips] Fix c.<cc>.<fmt> instruction definition."Simon Dardis2016-09-091-2/+1
| | | | | | | This reverts commit r281022. Mips buildbot broke, due to unhandled register class FCC. llvm-svn: 281033
* [mips] Fix c.<cc>.<fmt> instruction definition.Simon Dardis2016-09-091-1/+2
| | | | | | | | | | | | | | | As part of this effort, remove MipsFCmp nodes and use tablegen patterns rather than custom lowering through C++. Unexpectedly, this improves codesize for microMIPS as previous floating point setcc expansions would materialize 0 and 1 into GPRs before using the relevant mov[tf].[sd] instruction. Now $zero is used directly. Reviewers: dsanders, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23118 llvm-svn: 281022
* [mips][microMIPS] Implement DBITSWAP, DLSA and LWUPC and add tests for AUI ↵Hrvoje Varga2016-09-081-0/+4
| | | | | | | | instructions Differential Revision: https://reviews.llvm.org/D16452 llvm-svn: 280909
* [mips] MIPS32R6 compact branch supportDaniel Sanders2016-03-141-1/+6
| | | | | | | | | | | | | | | | | | | | | | | Summary: MIPSR6 introduces a class of branches called compact branches. Unlike the traditional MIPS branches which have a delay slot, compact branches do not have a delay slot. The instruction following the compact branch is only executed if the branch is not taken and must not be a branch. It works by generating compact branches for MIPS32R6 when the delay slot filler cannot fill a delay slot. Then, inspecting the generated code for forbidden slot hazards (a compact branch with an adjacent branch or other CTI) and inserting nops to clear this hazard. Patch by Simon Dardis. Reviewers: vkalintiris, dsanders Subscribers: MatzeB, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16353 llvm-svn: 263444
* [mips] Add support for branch-likely pseudo-instructionsZoran Jovanovic2015-09-151-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D10537 llvm-svn: 247697
* [mips] Added support for the ERETNC instruction.Vasileios Kalintiris2015-07-201-3/+3
| | | | | | | | | | | | | | Summary: This required adding the instruction predicate HasMips32r5. Patch by Scott Egerton. Reviewers: dsanders, vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11136 llvm-svn: 242666
* [mips] Add new format for dmtc2/dmfc2 for Octeon CPUs.Kai Nacke2015-05-281-0/+12
| | | | | | | | | | | | | Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor. E.g. dmtc2 rt,0x4057 starts calculation of sha-1. I had to introduce a new deconding namespace to avoid a decoding conflict. Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D10083 llvm-svn: 238439
* [mips][microMIPSr6] Implement mips32 to microMIPSr6 mapping supportZoran Jovanovic2015-04-221-0/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D8661 llvm-svn: 235505
* [mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132Kai Nacke2015-01-201-0/+13
| | | | | | | | | This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
* [mips] Add synci instruction.Daniel Sanders2014-11-271-0/+14
| | | | | | | | | | | | | | Patch by Amaury Pouly Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6421 llvm-svn: 222899
* [mips][microMIPS] Implement SDBBP and RDHWR instructions.Jozef Kolek2014-11-191-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D5240 llvm-svn: 222347
* Revert: r215698 - Current implementation of c.cond.fmt instructions only ↵Daniel Sanders2014-08-171-2/+1
| | | | | | | | | | | accept default cc0 register... It causes a number of regressions when -fintegrated-as is enabled. This happens because there are codegen-only instructions that incorrectly uses the first operand as the encoding for the $fcc register. The regressions do not occur when -via-file-asm is also given. llvm-svn: 215847
* Current implementation of c.cond.fmt instructions only accept default cc0 ↵Vladimir Medic2014-08-151-1/+2
| | | | | | register. This patch enables the instruction to accept other fcc registers. The aliases with default fcc0 registers are also defined. llvm-svn: 215698
* [mips] Added support for assembling sdbbp.Daniel Sanders2014-06-241-0/+10
| | | | | | | | | | Summary: This instruction is re-encoded in MIPS32r6/MIPS64r6 without changing the restrictions. We hadn't implemented it for earlier ISA's so it has been added to those too. Differential Revision: http://reviews.llvm.org/D4265 llvm-svn: 211590
* [mips] Add cache and pref instructionsDaniel Sanders2014-06-131-0/+14
| | | | | | | | | | | | | | | | | | | Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 llvm-svn: 210900
* [mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register ↵Matheus Almeida2014-06-111-0/+28
| | | | | | | | | | | | | | with Hazard Barrier). Summary: These instructions are available in ISAs >= mips32/mips64. For mips32r6/mips64r6, jr.hb has a new encoding format. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4019 llvm-svn: 210654
* [mips] Implement tlbp, tlbr, tlbwi, and tlbwrDaniel Sanders2014-05-081-0/+9
| | | | | | | | | | Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3571 llvm-svn: 208301
* [mips] Split Instruction.Predicates into smaller lists and re-join them with ↵Daniel Sanders2014-05-071-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | !listconcat Summary: The overall idea is to chop the Predicates list into subsets that are usually overridden independently. This allows subclasses to partially override the predicates of their superclasses without having to re-add all the existing predicates. This patch starts the process by moving HasStdEnc into a new EncodingPredicates list and almost everything else into AdditionalPredicates. It has revealed a couple likely bugs where 'let Predicates' has removed the HasStdEnc predicate. No functional change (confirmed by diffing tablegen-erated files). Depends on D3549, D3506 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3550 llvm-svn: 208184
* [mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu.Kai Nacke2014-04-041-0/+14
| | | | | | | | | This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205631
* [mips] Implement ehb, ssnop, and pause in assemblerDaniel Sanders2014-04-031-0/+11
| | | | | | | | | | | | Summary: Add negative tests for pause Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3246 llvm-svn: 205537
* [mips] Add more Octeon cnMips instructionsKai Nacke2014-04-021-0/+16
| | | | | | | | | | | | Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
* [mips] Add Octeon cnMips instructions mtmX and mtpXKai Nacke2014-04-011-0/+11
| | | | | | | | | Adds the Octeon cnMips instructions "load multiplier register MPLx" and "load product register Px". Includes tests. Reviews by: Daniel.Sanders@imgtec.com llvm-svn: 205343
* [MIPS] Add cpu octeon and some instructionsKai Nacke2014-03-201-0/+29
| | | | | | | | | | The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
* Implementation of microMIPS 16-bit instructions MOVE and JALR.Zoran Jovanovic2014-03-201-1/+1
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D3112 llvm-svn: 204325
* Support for microMIPS FPU instructions 2.Zoran Jovanovic2013-12-251-3/+3
| | | | llvm-svn: 198009
* Support for microMIPS FPU instructions 1.Zoran Jovanovic2013-12-201-7/+7
| | | | llvm-svn: 197815
* Support for microMIPS control instructions.Zoran Jovanovic2013-12-191-5/+15
| | | | llvm-svn: 197696
* Support for microMIPS trap instruction with immediate operands.Zoran Jovanovic2013-11-131-1/+1
| | | | llvm-svn: 194569
* Support for microMIPS trap instructions 1.Zoran Jovanovic2013-11-071-1/+1
| | | | llvm-svn: 194205
* Support for microMIPS branch instructions.Zoran Jovanovic2013-11-041-3/+3
| | | | llvm-svn: 193992
* Support for microMIPS jump instructionsZoran Jovanovic2013-10-291-2/+2
| | | | llvm-svn: 193623
* Fixed bug when generating Load Upper Immediate microMIPS instruction.Zoran Jovanovic2013-09-141-1/+1
| | | | llvm-svn: 190746
* Support for misc microMIPS instructions.Zoran Jovanovic2013-09-141-3/+3
| | | | llvm-svn: 190744
* [mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, ↵Akira Hatanaka2013-09-061-11/+0
| | | | | | | | which is equivalent to "beq $zero, $zero, offset". llvm-svn: 190220
* This patch adds support for microMIPS Move to/from HI/LO instructions. Test ↵Vladimir Medic2013-09-061-2/+2
| | | | | | cases are included in patch. llvm-svn: 190152
* This patch adds support for microMIPS Move Conditional instructions. Test ↵Vladimir Medic2013-09-061-1/+1
| | | | | | cases are included in patch. llvm-svn: 190148
* This patch implements trap instructions for mips. The test cases are added.Vladimir Medic2013-08-261-0/+11
| | | | llvm-svn: 189213
* This patch implements ei and di instructions for mips. Test cases are added.Vladimir Medic2013-08-121-0/+18
| | | | llvm-svn: 188176
* Moving definition of MnemonicContainsDot field from class Instruction to ↵Vladimir Medic2013-08-011-1/+0
| | | | | | class AsmParser as suggested. llvm-svn: 187569
* [mips] Delete instruction format for "bal".Akira Hatanaka2013-07-301-11/+0
| | | | llvm-svn: 187443
* [mips] Fix FP conditional move instructions to have explicit FP condition codeAkira Hatanaka2013-07-261-2/+4
| | | | | | register operands. llvm-svn: 187242
* [mips] Fix FP branch instructions to have explicit FP condition code registerAkira Hatanaka2013-07-261-1/+2
| | | | | | operands. llvm-svn: 187238
* Implement eret and deret(return from exception) instructions for Mips. Test ↵Vladimir Medic2013-07-171-0/+13
| | | | | | examples are given. llvm-svn: 186507
* This patch represents Mips utilization of r186388 code that alows asm ↵Vladimir Medic2013-07-161-0/+5
| | | | | | matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. llvm-svn: 186397
* Add support for Mips break and syscall insructions. The corresponding test ↵Vladimir Medic2013-07-121-0/+28
| | | | | | cases are added. llvm-svn: 186151
* Reverting commit r185999 due to buildboot failure.Vladimir Medic2013-07-101-28/+0
| | | | llvm-svn: 186000
* Add support for Mips break and syscall insructions. The corresponding test ↵Vladimir Medic2013-07-101-0/+28
| | | | | | cases are added. llvm-svn: 185999
* [mips] Trap on integer division by zero.Akira Hatanaka2013-05-201-0/+14
| | | | | | | By default, a teq instruction is inserted after integer divide. No divide-by-zero checks are performed if option "-mnocheck-zero-division" is used. llvm-svn: 182306
* [mips] Add definitions of micromips load and store instructions.Akira Hatanaka2013-04-251-1/+1
| | | | | | Patch by Zoran Jovanovic. llvm-svn: 180241
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