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| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-09-09 11:06:01 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-09-09 11:06:01 +0000 |
| commit | ba92b034bf561b68e1c591e17c99dbdde0485f15 (patch) | |
| tree | 9738ffa262e2fa1d377704f3d2c07532e221146f /llvm/lib/Target/Mips/MipsInstrFormats.td | |
| parent | 817bc16d19447328ee9cedf51a8f85cd4fa2fc14 (diff) | |
| download | bcm5719-llvm-ba92b034bf561b68e1c591e17c99dbdde0485f15.tar.gz bcm5719-llvm-ba92b034bf561b68e1c591e17c99dbdde0485f15.zip | |
Revert "[mips] Fix c.<cc>.<fmt> instruction definition."
This reverts commit r281022. Mips buildbot broke, due to unhandled register
class FCC.
llvm-svn: 281033
Diffstat (limited to 'llvm/lib/Target/Mips/MipsInstrFormats.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrFormats.td | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td index ded3e324286..1437fb75434 100644 --- a/llvm/lib/Target/Mips/MipsInstrFormats.td +++ b/llvm/lib/Target/Mips/MipsInstrFormats.td @@ -829,7 +829,6 @@ class BC1F_FM<bit nd, bit tf> : StdArch { class CEQS_FM<bits<5> fmt> : StdArch { bits<5> fs; bits<5> ft; - bits<3> fcc; bits<4> cond; bits<32> Inst; @@ -838,7 +837,7 @@ class CEQS_FM<bits<5> fmt> : StdArch { let Inst{25-21} = fmt; let Inst{20-16} = ft; let Inst{15-11} = fs; - let Inst{10-8} = fcc; + let Inst{10-8} = 0; // cc let Inst{7-4} = 0x3; let Inst{3-0} = cond; } |
