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path: root/llvm/lib/Target/Mips/MipsISelLowering.cpp
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* [mips] Use 64-bit registers to return an sret pointer if target ABI is N64.Akira Hatanaka2012-10-191-2/+4
| | | | llvm-svn: 166344
* [mips] Add code to do tail call optimization.Akira Hatanaka2012-10-191-5/+39
| | | | | | | Currently, it is enabled only if option "enable-mips-tail-calls" is given and all of the callee's arguments are passed in registers. llvm-svn: 166342
* [mips] Delete MipsFunctionInfo::MaxCallFrameSize which is no longer used.Akira Hatanaka2012-10-191-4/+0
| | | | llvm-svn: 166339
* Add node and enum for mips tail call.Akira Hatanaka2012-10-191-0/+1
| | | | llvm-svn: 166318
* Implement MipsTargetLowering::CanLowerReturn.Akira Hatanaka2012-10-101-1/+16
| | | | | | Patch by Sasa Stankovic. llvm-svn: 165585
* Patch for integer multiply, signed/unsigned, long/long long.Reed Kotler2012-10-051-2/+4
| | | | llvm-svn: 165322
* MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos ↵Akira Hatanaka2012-09-271-0/+66
| | | | | | Field instruction. llvm-svn: 164751
* MIPS DSP: all the remaining instructions which read or write accumulators.Akira Hatanaka2012-09-271-0/+60
| | | | llvm-svn: 164750
* MIPS DSP: add support for extract-word instructions.Akira Hatanaka2012-09-271-0/+87
| | | | llvm-svn: 164749
* Add MIPS DSP register classes. Set actions of DSP vector operations and overrideAkira Hatanaka2012-09-211-0/+39
| | | | | | TargetLowering's callback functions. llvm-svn: 164431
* SelectionDAG node enums for MIPS DSP nodes.Akira Hatanaka2012-09-211-0/+14
| | | | llvm-svn: 164430
* Handled unaligned load/stores properly in Mips16 Akira Hatanaka2012-09-151-2/+7
| | | | | | Patch by Reed Kotler. llvm-svn: 163956
* Misc.Akira Hatanaka2012-09-121-3/+6
| | | | | | | | | 1. Remove RA from list of allocatable registers 2. Enable d,y,r constraint inline assembly instructions Patch by Reed Kotler. llvm-svn: 163753
* Fix PR11985Michael Liao2012-09-121-4/+4
| | | | | | | | | | | - BlockAddress has no support of BA + offset form and there is no way to propagate that offset into machine operand; - Add BA + offset support and a new interface 'getTargetBlockAddress' to simplify target block address forming; - All targets are modified to use new interface and X86 backend is enhanced to support BA + offset addressing. llvm-svn: 163743
* Stop casting away const qualifier needlessly.Roman Divacky2012-09-051-1/+1
| | | | llvm-svn: 163258
* Add register Mips::GP to the list of reserved registers if target is bare-metalAkira Hatanaka2012-08-221-2/+2
| | | | | | | | to prevent it from being clobbered. mips uses $gp to access small data section. This bug was originally reported by Carl Norum. llvm-svn: 162340
* Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering.Akira Hatanaka2012-07-311-50/+3
| | | | | | | The frame object which points to the dynamically allocated area will not be needed after changes are made to cease reserving call frames. llvm-svn: 161076
* When store nodes or memcpy nodes are created to copy the function callAkira Hatanaka2012-07-311-46/+31
| | | | | | | arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and integer offset operands rather than frame object operands. llvm-svn: 161068
* Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined asAkira Hatanaka2012-07-311-2/+0
| | | | | | | | | single-precision load and store. Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect to map unaligned floating point load/store nodes to these instructions. llvm-svn: 161063
* Pass the correct call frame size to callseq_start node. This is needed toAkira Hatanaka2012-07-261-15/+10
| | | | | | | replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with the one MachineFrameInfo has. llvm-svn: 160841
* Fix call setup for PIC.Akira Hatanaka2012-07-261-5/+13
| | | | | | Patch by Reed Kotler. llvm-svn: 160774
* Add basic ability to setup call frame, and make procedure calls.Akira Hatanaka2012-07-231-1/+4
| | | | | | | | Hello world will compile and execute with this patch. Patch by Reed Kotler. llvm-svn: 160651
* Revert accidental commit.Akira Hatanaka2012-07-211-4/+1
| | | | llvm-svn: 160598
* Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.Akira Hatanaka2012-07-211-1/+4
| | | | | | Test case will be added later when long branch patch is checked in. llvm-svn: 160597
* Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.Akira Hatanaka2012-07-111-3/+16
| | | | llvm-svn: 160064
* Lower RETURNADDR node in Mips backend.Akira Hatanaka2012-07-111-0/+18
| | | | | | Patch by Sasa Stankovic. llvm-svn: 160031
* Make register Mips::RA allocatable if not in mips16 mode.Akira Hatanaka2012-07-101-5/+4
| | | | llvm-svn: 159971
* mips32 long long register inline asm constraint support.Jack Carter2012-07-021-0/+2
| | | | | | | inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll) llvm-svn: 159625
* Revert " mips32 long long register inline asm constraint support." asEric Christopher2012-07-021-2/+0
| | | | | | | | it appears to be breaking the bots. This reverts commit 1b055ce320fa13f6f1ac81670d11b45e01f79876. llvm-svn: 159619
* mips32 long long register inline asm constraint support.Jack Carter2012-07-021-0/+2
| | | | | | | inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll) llvm-svn: 159610
* Fix coding style violations. Remove white spaces and tabs.Akira Hatanaka2012-06-141-44/+44
| | | | llvm-svn: 158471
* Implement a DAGCombine in MipsISelLowering.cpp which transforms the followingAkira Hatanaka2012-06-131-0/+30
| | | | | | | | | | pattern: (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) "tjt" is a TargetJumpTable node. llvm-svn: 158419
* Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp.Akira Hatanaka2012-06-131-0/+12
| | | | llvm-svn: 158414
* Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp.Akira Hatanaka2012-06-131-11/+6
| | | | llvm-svn: 158413
* Implement fastcc calling convention for MIPS.Akira Hatanaka2012-06-131-3/+7
| | | | llvm-svn: 158410
* Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node isAkira Hatanaka2012-06-041-1/+2
| | | | | | inserted after the shift-left-logical node. llvm-svn: 157937
* MIPS TLS: use the model selected by TargetMachine::getTLSModel().Hans Wennborg2012-06-041-3/+4
| | | | | | This was mostly done already in r156162, but I missed one place. llvm-svn: 157929
* remove an unused variable.Chris Lattner2012-06-021-1/+1
| | | | llvm-svn: 157872
* Set operation actions for load/store nodes in the Mips backend.Akira Hatanaka2012-06-021-0/+11
| | | | llvm-svn: 157866
* Define functions MipsTargetLowering::LowerLOAD and LowerSTORE whichAkira Hatanaka2012-06-021-0/+138
| | | | | | custom-lower unaligned load and store nodes. llvm-svn: 157864
* Define Mips specific unaligned load/store nodes.Akira Hatanaka2012-06-021-0/+8
| | | | llvm-svn: 157863
* Expand unaligned i16 loads/stores for the Mips backend.Akira Hatanaka2012-06-021-1/+0
| | | | | | | | This is the first of a series of patches which make changes to the backend to emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction selection. llvm-svn: 157862
* Cleanup and factoring of mips16 tablegen classes. Make register classesAkira Hatanaka2012-05-311-0/+5
| | | | | | | | | CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16 jalr instruction. Patch by Reed Kotler. llvm-svn: 157730
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-251-9/+14
| | | | | | | | | | to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
* Make the following changes in MipsISelLowering.cpp:Akira Hatanaka2012-05-121-8/+8
| | | | | | | | | - Stop creating stack frame objects needed for saving $gp. - Insert a node that copies the global pointer register to register $gp before the call node. This will ensure $gp is valid at the entry of the called function. llvm-svn: 156692
* Expand 64-bit shifts if target ABI is O32.Akira Hatanaka2012-05-091-3/+81
| | | | llvm-svn: 156457
* Add support for the 'x' constraint.Eric Christopher2012-05-071-1/+8
| | | | | | Patch by Jack Carter. llvm-svn: 156295
* Add support for the 'l' constraint.Eric Christopher2012-05-071-0/+7
| | | | | | Patch by Jack Carter. llvm-svn: 156294
* Add support for the 'c' constraint.Eric Christopher2012-05-071-1/+13
| | | | | | Patch by Jack Carter. llvm-svn: 156293
* Add support for the 'P' constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156292
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