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path: root/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
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* Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td andAkira Hatanaka2012-09-151-0/+9
| | | | | | | | | | use load/store fragments defined in TargetSelectionDAG.td in place of them. Unaligned loads/stores are either expanded or lowered to target-specific nodes, so instruction selection should see only aligned load/store nodes. No changes in functionality. llvm-svn: 163960
* In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if itsAkira Hatanaka2012-08-241-2/+3
| | | | | | second operand is MipsISD::GPRel. llvm-svn: 162584
* Don't modify MO while use_iterator is still pointing to it.Jakob Stoklund Olesen2012-08-091-3/+4
| | | | llvm-svn: 161626
* Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined asAkira Hatanaka2012-07-311-15/+2
| | | | | | | | | single-precision load and store. Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect to map unaligned floating point load/store nodes to these instructions. llvm-svn: 161063
* Eliminate the stack slot used to save the global base register.Akira Hatanaka2012-07-251-32/+12
| | | | | | | | The long branch pass (fixed in r160601) no longer uses the global base register to compute addresses of branch destinations, so it is not necessary to reserve a slot on the stack. llvm-svn: 160703
* Add basic ability to setup call frame, and make procedure calls.Akira Hatanaka2012-07-231-8/+26
| | | | | | | | Hello world will compile and execute with this patch. Patch by Reed Kotler. llvm-svn: 160651
* Revert accidental commit.Akira Hatanaka2012-07-211-26/+8
| | | | llvm-svn: 160598
* Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.Akira Hatanaka2012-07-211-8/+26
| | | | | | Test case will be added later when long branch patch is checked in. llvm-svn: 160597
* Silence uninitialized variable warning in MipsISelDAGToDAG.cpp.Akira Hatanaka2012-06-271-1/+1
| | | | llvm-svn: 159243
* Fix bug in computation of stack size in MipsFrameLowering.cpp.Akira Hatanaka2012-06-271-0/+4
| | | | llvm-svn: 159240
* 1. fix null program output after some other changesAkira Hatanaka2012-06-211-1/+8
| | | | | | | | | 2. re-enable null.ll test 3. fix some minor style violations Patch by Reed Kotler. llvm-svn: 158935
* Fix coding style violations. Remove white spaces and tabs.Akira Hatanaka2012-06-141-3/+5
| | | | llvm-svn: 158471
* In MipsISelDAGToDAG.cpp, store the global base register to a stack frame object.Akira Hatanaka2012-06-141-3/+10
| | | | | | | Long-branches need access to the global base register to get the destination address. llvm-svn: 158428
* Implement a DAGCombine in MipsISelLowering.cpp which transforms the followingAkira Hatanaka2012-06-131-4/+4
| | | | | | | | | | pattern: (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) "tjt" is a TargetJumpTable node. llvm-svn: 158419
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-021-1/+1
| | | | llvm-svn: 157885
* Insert instructions to the entry basic block which initializes the globalAkira Hatanaka2012-05-121-35/+52
| | | | | | | | | | | | | | | | | | pointer register. This is the first of the series of patches which clean up the way global pointer register is used. The patches will make the following improvements: - Make $gp an allocatable temporary register rather than reserving it. - Use a virtual register as the global pointer register and let the register allocator decide which register to assign to it or whether spill/reloads are needed. - Make sure $gp is valid at the entry of a called function, which is necessary for functions using lazy binding. - Remove the need for emitting .cprestore and .cpload directives. llvm-svn: 156671
* Do not replace operands of pseudo instructions with register $zero.Akira Hatanaka2012-05-111-1/+2
| | | | llvm-svn: 156663
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-1/+2
| | | | | | since they are equivalent. llvm-svn: 155188
* Add T9 to the list of live-in registers of the entry basic block. Akira Hatanaka2012-03-271-0/+2
| | | | llvm-svn: 153497
* This patch eliminates redundant instructions that produce 0.Akira Hatanaka2012-03-081-1/+50
| | | | | | | | | | | | For example, the first instruction in the code below can be eliminated if the use of $vr0 is replaced with $zero: addiu $vr0, $zero, 0 add $vr2, $vr1, $vr0 add $vr2, $vr1, $zero llvm-svn: 152280
* Fix bugs which were introduced when support for base+index floating point loadsAkira Hatanaka2012-03-011-5/+19
| | | | | | | | | | | and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. llvm-svn: 151843
* remove blanks, and some code formatJia Liu2012-02-281-10/+10
| | | | llvm-svn: 151625
* Do not reserve $gp as a dedicated global base register if the target ABI is ↵Akira Hatanaka2012-02-281-1/+2
| | | | | | not O32. llvm-svn: 151614
* Add support for floating point base register + offset register addressing modeAkira Hatanaka2012-02-281-2/+9
| | | | | | load and store instructions. llvm-svn: 151611
* Add an option to use a virtual register as the global base register instead ofAkira Hatanaka2012-02-241-4/+86
| | | | | | | | | | | | | | | | | | | | | | | | | reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
* remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.Jia Liu2012-02-171-1/+1
| | | | llvm-svn: 150805
* add Emacs tag and fix some comment error in file headersJia Liu2012-02-171-1/+1
| | | | llvm-svn: 150775
* Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. Akira Hatanaka2012-01-251-0/+42
| | | | | | | Add a test case to show fewer instructions are needed to load an immediate with the new way of loading immediates. llvm-svn: 148908
* Fix uninitialized variable warning.Chad Rosier2012-01-061-1/+1
| | | | llvm-svn: 147676
* Add function MipsDAGToDAGISel::SelectMULT and factor out code that generatesAkira Hatanaka2011-12-201-37/+47
| | | | | | | nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU nodes. llvm-svn: 147008
* Fix indentation.Akira Hatanaka2011-12-201-115/+115
| | | | llvm-svn: 147007
* Add code in MipsDAGToDAGISel for selecting constant +0.0.Akira Hatanaka2011-12-201-0/+6
| | | | | | MIPS64 can generate constant +0.0 with a single DMTC1 instruction. llvm-svn: 146999
* Revert part of r146995 that was accidentally commmitted.Akira Hatanaka2011-12-201-6/+0
| | | | llvm-svn: 146996
* 32-to-64-bit sign extension pattern.Akira Hatanaka2011-12-201-0/+6
| | | | llvm-svn: 146995
* Tidy up. Simplify logic. No functional change intended.Akira Hatanaka2011-12-191-4/+6
| | | | llvm-svn: 146896
* Remove the restriction on the first operand of the add node in SelectAddr.Akira Hatanaka2011-12-191-3/+1
| | | | | | | | | | | | | | | | | | This change reduces the number of instructions generated. For example, (load (add (sub $n0, $n1), (MipsLo got(s)))) results in the following sequence of instructions: 1. sub $n2, $n0, $n1 2. lw got(s)($n2) Previously, three instructions were needed. 1. sub $n2, $n0, $n1 2. addiu $n3, $n2, got(s) 3. lw 0($n3) llvm-svn: 146888
* Rename WrapperPIC. It is now used for both pic and static.Akira Hatanaka2011-12-091-1/+1
| | | | llvm-svn: 146232
* Implement 64-bit support for thread local storage handling.Akira Hatanaka2011-12-081-17/+23
| | | | | | | | | | - Modify lowering of global TLS address nodes. - Modify isel of ThreadPointer. - Wrap target global TLS address nodes that are operands of loads with WrapperPIC. - Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be substituted with other existing nodes. llvm-svn: 146175
* Fix comment.Akira Hatanaka2011-12-071-2/+1
| | | | llvm-svn: 146063
* Fix comment.Akira Hatanaka2011-12-071-1/+1
| | | | llvm-svn: 146062
* Fix 64-bit immediate patterns.Akira Hatanaka2011-12-071-2/+2
| | | | llvm-svn: 146059
* Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too.Akira Hatanaka2011-10-111-7/+10
| | | | llvm-svn: 141615
* Add support for 64-bit integer multiply instructions.Akira Hatanaka2011-10-031-4/+14
| | | | llvm-svn: 141017
* Change the names of functions isMips* to hasMips*.Akira Hatanaka2011-09-201-1/+1
| | | | llvm-svn: 140214
* Fix handling of double precision loads and stores when Mips1 is targeted. Akira Hatanaka2011-08-161-139/+0
| | | | | | | | | | | | | | | Mips1 does not support double precision loads or stores, therefore two single precision loads or stores must be used in place of these instructions. This patch treats double precision loads and stores as if they are legal instructions until MCInstLowering, instead of generating the single precision instructions during instruction selection or Prolog/Epilog code insertion. Without the changes made in this patch, llc produces code that has the same problem described in r137484 or bails out when MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before register allocation. llvm-svn: 137711
* When constant double 0.0 is lowered, make sure 0 is copied directly from an Akira Hatanaka2011-08-121-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | integer register to a floating point register. It is not valid to interpret the value of a floating pointer register as part of a double precision floating point value after a single precision floating point computational or move instruction stores its result to the register. - In the test case, the following code is generated before this patch is applied: mtc1 $zero, $f2 ; unformatted copy to $f2 mov.s $f0, $f2 ; $f0 is in single format sdc1 $f12, 0($sp) mov.s $f1, $f2 ; $f1 is in single format c.eq.d $f12, $f0 ; $f0 cannot be interpreted as double - The following code is generated after this patch is applied: mtc1 $zero, $f0 ; unformatted copy to $f0 mtc1 $zero, $f1 ; unformatted copy to $f1 c.eq.d $f12, $f0 ; $f0 can be interpreted as double Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and provided the test case. llvm-svn: 137484
* Reverse order of operands of address operand mem so that the base operand comesAkira Hatanaka2011-07-071-7/+7
| | | | | | | before the offset. This change will enable simplification of function MipsRegisterInfo::eliminateFrameIndex. llvm-svn: 134625
* Prevent generation of redundant addiu instructions that compute address of Akira Hatanaka2011-06-241-1/+2
| | | | | | static variables or functions. llvm-svn: 133803
* Re-apply 132758 and 132768 which were speculatively reverted in 132777. Akira Hatanaka2011-06-211-0/+12
| | | | llvm-svn: 133494
* Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.Eric Christopher2011-06-091-12/+0
| | | | llvm-svn: 132777
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