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authorAkira Hatanaka <ahatanaka@mips.com>2012-06-21 20:39:10 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2012-06-21 20:39:10 +0000
commit765c312314536069dd52ef96144cb8d8d25e1eb1 (patch)
tree41eaf29c9c49039d02da4d631dc258d7f3b42a41 /llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
parent07604703719d84f247a75620ab27748f11ad6f11 (diff)
downloadbcm5719-llvm-765c312314536069dd52ef96144cb8d8d25e1eb1.tar.gz
bcm5719-llvm-765c312314536069dd52ef96144cb8d8d25e1eb1.zip
1. fix null program output after some other changes
2. re-enable null.ll test 3. fix some minor style violations Patch by Reed Kotler. llvm-svn: 158935
Diffstat (limited to 'llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp')
-rw-r--r--llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp9
1 files changed, 8 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
index 4236f74dea3..15e745f7ea1 100644
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -125,7 +125,10 @@ void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
- int FI = MipsFI->initGlobalRegFI();
+ int FI; // should initialize this to some kind of null
+
+ if (!Subtarget.inMips16Mode())
+ FI= MipsFI->initGlobalRegFI();
const TargetRegisterClass *RC = Subtarget.isABI_N64() ?
(const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
@@ -187,6 +190,10 @@ void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
assert(Subtarget.isABI_O32());
+ if (Subtarget.inMips16Mode())
+ return; // no need to load GP. It can be calculated anywhere
+
+
// For O32 ABI, the following instruction sequence is emitted to initialize
// the global base register:
//
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