summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Mips/MipsFrameLowering.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [mips] Use register scavenging with MSA.Simon Dardis2017-11-021-21/+14
| | | | | | | | | | | | | | | | | MSA stores and loads to the stack are more likely to require an emergency GPR spill slot due to the smaller offsets available with those instructions. Handle this by overestimating the size of the stack by determining the largest offset presuming that all callee save registers are spilled and accounting of incoming arguments when determining whether an emergency spill slot is required. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39056 llvm-svn: 317204
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-1/+1
| | | | | | | | | | | | | | | 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 llvm-svn: 301221
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-13/+13
| | | | | | | getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
* [NFC] Header cleanupMehdi Amini2016-04-181-1/+0
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* Change eliminateCallFramePseudoInstr() to return an iteratorHans Wennborg2016-03-311-2/+2
| | | | | | | | | | | | | | | | | | | | | This will become necessary in a subsequent change to make this method merge adjacent stack adjustments, i.e. it might erase the previous and/or next instruction. It also greatly simplifies the calls to this function from Prolog- EpilogInserter. Previously, that had a bunch of logic to resume iteration after the call; now it just continues with the returned iterator. Note that this changes the behaviour of PEI a little. Previously, it attempted to re-visit the new instruction created by eliminateCallFramePseudoInstr(). That code was added in r36625, but I can't see any reason for it: the new instructions will obviously not be pseudo instructions, they will not have FrameIndex operands, and we have already accounted for the stack adjustment. Differential Revision: http://reviews.llvm.org/D18627 llvm-svn: 265036
* [mips] Remove redundant inclusions of MipsAnalyzeImmediate.hDaniel Sanders2016-02-031-1/+0
| | | | llvm-svn: 259655
* Update to use new name alignTo().Rui Ueyama2016-01-141-5/+5
| | | | llvm-svn: 257804
* [mips] Add support for dynamic stack realignment.Vasileios Kalintiris2015-06-021-3/+14
| | | | | | | | | | | | | | | | | | | | Summary: With this change we are able to realign the stack dynamically, whenever it contains objects with alignment requirements that are larger than the alignment specified from the given ABI. We have to use the $fp register as the frame pointer when we perform dynamic stack realignment. In complex stack frames, with variably-sized objects, we reserve additionally the callee-saved register $s7 as the base pointer in order to reference locals. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8633 llvm-svn: 238829
* [mips] Implement eliminateCallFramePseudoInstr() in MipsFrameLowering. NFC.Vasileios Kalintiris2015-04-021-0/+17
| | | | | | | | | | | | | | | | | Summary: Avoid duplicate code in Mips16FrameLowering and MipsSEFrameLowering by providing an implementation of the eliminateCallFramePseudoInstr() function from their base class. Depends on D8640. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8641 llvm-svn: 233909
* Remove most of the TargetMachine::getSubtarget/getSubtargetImplEric Christopher2015-01-291-1/+1
| | | | | | | | | calls that don't take a Function argument from Mips. Notable exceptions: the AsmPrinter and MipsTargetObjectFile. The latter needs to be fixed, and the former will be fixed when the general AsmPrinter changes happen. llvm-svn: 227512
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-2/+1
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-1/+2
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* FrameLowering depends only upon the Subtarget, so only take a subtargetEric Christopher2014-07-181-3/+2
| | | | | | during initialization. llvm-svn: 213429
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-041-1/+1
| | | | llvm-svn: 205610
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-2/+2
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-3/+3
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* [mips] Add function MipsFrameLowering::estimateStackSize.Akira Hatanaka2012-11-021-0/+34
| | | | | | | This function estimates stack size and will be called before PrologEpilogInserter scans the callee-saved registers. llvm-svn: 167313
* Move TargetData to DataLayout.Micah Villmow2012-10-081-1/+1
| | | | llvm-svn: 165402
* Move the code that creates instances of MipsInstrInfo and MipsFrameLowering outAkira Hatanaka2012-08-021-0/+9
| | | | | | of MipsTargetMachine.cpp. llvm-svn: 161191
* Add definitions of two subclasses of MipsFrameLowering, Mips16FrameLowering andAkira Hatanaka2012-07-311-201/+0
| | | | | | | | | | MipsSEFrameLowering. Implement MipsSEFrameLowering::hasReservedCallFrame. Call frames will not be reserved if there is a call with a large call frame or there are variable sized objects on the stack. llvm-svn: 161090
* Let PEI::calculateFrameObjectOffsets compute the final stack size rather thanAkira Hatanaka2012-07-311-10/+1
| | | | | | computing it in MipsFrameLowering::emitPrologue. llvm-svn: 161078
* When store nodes or memcpy nodes are created to copy the function callAkira Hatanaka2012-07-311-2/+1
| | | | | | | arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and integer offset operands rather than frame object operands. llvm-svn: 161068
* Eliminate the stack slot used to save the global base register.Akira Hatanaka2012-07-251-5/+1
| | | | | | | | The long branch pass (fixed in r160601) no longer uses the global base register to compute addresses of branch destinations, so it is not necessary to reserve a slot on the stack. llvm-svn: 160703
* Add basic ability to setup call frame, and make procedure calls.Akira Hatanaka2012-07-231-5/+16
| | | | | | | | Hello world will compile and execute with this patch. Patch by Reed Kotler. llvm-svn: 160651
* Revert accidental commit.Akira Hatanaka2012-07-211-16/+5
| | | | llvm-svn: 160598
* Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.Akira Hatanaka2012-07-211-5/+16
| | | | | | Test case will be added later when long branch patch is checked in. llvm-svn: 160597
* Lower RETURNADDR node in Mips backend.Akira Hatanaka2012-07-111-5/+12
| | | | | | Patch by Sasa Stankovic. llvm-svn: 160031
* Make register Mips::RA allocatable if not in mips16 mode.Akira Hatanaka2012-07-101-10/+22
| | | | llvm-svn: 159971
* Fix bug in computation of stack size in MipsFrameLowering.cpp.Akira Hatanaka2012-06-271-3/+6
| | | | llvm-svn: 159240
* 1. fix null program output after some other changesAkira Hatanaka2012-06-211-1/+2
| | | | | | | | | 2. re-enable null.ll test 3. fix some minor style violations Patch by Reed Kotler. llvm-svn: 158935
* Fix coding style violations. Remove white spaces and tabs.Akira Hatanaka2012-06-141-1/+1
| | | | llvm-svn: 158471
* In MipsFrameLowering::emitPrologue and emitEpilogue, call Mips::loadImmediateAkira Hatanaka2012-06-141-39/+16
| | | | | | | | to load an immediate that does not fit into 16-bit. Also, take into consideration the global base register slot on the stack when computing the stack size. llvm-svn: 158430
* Fix some uses of getSubRegisters() to use getSubReg() instead.Jakob Stoklund Olesen2012-05-301-3/+2
| | | | | | | It is better to address sub-registers directly by name instead of relying on their position in the sub-register list. llvm-svn: 157703
* Make the following changes in MipsFrameLowering.cpp:Akira Hatanaka2012-05-121-32/+3
| | | | | | | | - Stop emitting instructions needed to initialize the global pointer register. - Stop emitting .cprestore directive. - Do not take into account the $gp save slot when computing stack size. llvm-svn: 156691
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-3/+2
| | | | | | since they are equivalent. llvm-svn: 155188
* Emit all directives except for ".cprestore" during asm printing rather than emitAkira Hatanaka2012-03-281-20/+18
| | | | | | | | | | | | | | | | them as machine instructions. Directives ".set noat" and ".set at" are now emitted only at the beginning and end of a function except in the case where they are emitted to enclose .cpload with an immediate operand that doesn't fit in 16-bit field or unaligned load/stores. Also, make the following changes: - Remove function isUnalignedLoadStore and use a switch-case statement to determine whether an instruction is an unaligned load or store. - Define helper function CreateMCInst which generates an instance of an MCInst from an opcode and a list of operands. llvm-svn: 153552
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-1/+1
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-1/+1
| | | | | | static data size. llvm-svn: 152016
* remove blanks, and some code formatJia Liu2012-02-281-12/+12
| | | | llvm-svn: 151625
* Add an option to use a virtual register as the global base register instead ofAkira Hatanaka2012-02-241-28/+11
| | | | | | | | | | | | | | | | | | | | | | | | | reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
* remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.Jia Liu2012-02-171-1/+1
| | | | llvm-svn: 150805
* Mark 64-bit register RA_64 unused too.Akira Hatanaka2012-01-251-4/+5
| | | | llvm-svn: 148918
* Modify MipsFrameLowering::emitPrologue and emitEpilogue.Akira Hatanaka2012-01-251-78/+68
| | | | | | | | | | | - Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit. - Change the types of variables so that they are sufficiently large to handle 64-bit pointers. - Emit instructions to set register $28 in a function prologue after instructions which store callee-saved registers have been emitted. llvm-svn: 148917
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-2/+2
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bitAkira Hatanaka2011-11-151-16/+20
| | | | | | registers and instructions when ABI is N64. llvm-svn: 144666
* Set nomacro before emitting the sequence of instructions that set global pointerAkira Hatanaka2011-11-151-3/+2
| | | | | | register. llvm-svn: 144665
* Remove variable that keeps the size of area used to save byval or variableAkira Hatanaka2011-11-141-1/+0
| | | | | | | | | | | argument registers on the callee's stack frame, along with functions that set and get it. It is not necessary to add the size of this area when computing stack size in emitPrologue, since it has already been accounted for in PEI::calculateFrameObjectOffsets. llvm-svn: 144549
* Mips MC object code emission improvements:Bruno Cardoso Lopes2011-11-111-0/+1
| | | | | | | | | | "With this patch we can now generate runnable Mips code through LLVM direct object emission. We have run numerous simple programs, both C and C++ and with -O0 and -O3 from the output. The code is not production ready, but quite useful for experimentation." Patch and message by Jack Carter llvm-svn: 144414
* Emit Mips64's sequence of instructions that set global register in prologue.Akira Hatanaka2011-11-111-1/+21
| | | | llvm-svn: 144367
OpenPOWER on IntegriCloud