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path: root/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
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* [NFC] Header cleanupMehdi Amini2016-04-181-2/+0
* RegisterScavenger: Take a reference as enterBasicBlock() argument.Matthias Braun2016-04-061-1/+1
* Remove windows line endings introduced by r252177. NFC.Tim Northover2015-11-051-21/+21
* [DebugInfo] Fix ARM/AArch64 prologue_end position. Related to D11268.Oleg Ranevskyy2015-11-051-21/+21
* [mips] Make sure that we don't adjust the stack pointer by zero amount.Vasileios Kalintiris2015-04-021-0/+3
* Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used.Benjamin Kramer2015-03-231-0/+1
* Remove the need to cache the subtarget in the Mips TargetRegisterInfoEric Christopher2015-03-121-2/+1
* Replace several 'assert(false' with 'llvm_unreachable' or fold a condition in...Craig Topper2015-01-051-4/+2
* Make InstrInfo depend only upon the Subtarget getting passed inEric Christopher2014-07-181-5/+4
* Remove commented out code.Eric Christopher2014-07-181-3/+0
* Clean up some style and formatting issues.Eric Christopher2014-07-181-33/+29
* [Modules] Make Support/Debug.h modular. This requires it to not changeChandler Carruth2014-04-211-0/+1
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-1/+1
* remove an uneeded statement (condition is covered by the statementReed Kotler2013-12-151-2/+0
* Last change for mips16 prolog/epilog cleanup and optimization.Reed Kotler2013-12-151-28/+48
* Distinguish and choose 16 or 32 bit forms of save/restore for Mips16.Reed Kotler2013-12-111-4/+8
* Next step in Mips16 prologue/epilogue cleanup.Reed Kotler2013-12-101-8/+22
* get rid of superfluous commentReed Kotler2013-12-091-1/+0
* Delete some old code used for testing that is not needed anymore.Reed Kotler2013-12-091-87/+33
* Make sure we mark these registers as defined. Previously was doneReed Kotler2013-12-081-6/+10
* Cleaning up of prologue/epilogue code for Mips16. First stepReed Kotler2013-12-081-4/+13
* Delete dead code.Reed Kotler2013-12-061-16/+0
* Make sure that for C++ emitting LwConstant32 pseudos, that it correspondsReed Kotler2013-11-241-2/+2
* Make all the conditional Mips 16 branches get initially set for theReed Kotler2013-11-151-0/+6
* Mips16InstrInfo.cpp: Use <cctype> instead of <ctype.h>NAKAMURA Takumi2013-11-131-2/+1
* Allow the code which returns the length for inline assembler to knowReed Kotler2013-11-131-1/+47
* Change the default branch instruction to be the 16 bit variety for mips16.Reed Kotler2013-11-121-1/+2
* Remove unused stdio.h includesDmitri Gribenko2013-08-181-3/+1
* [mips] Rename HIRegs and LORegs.Akira Hatanaka2013-08-141-2/+2
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-061-2/+2
* Clean up code for Mips16 large frame handling.Reed Kotler2013-08-041-28/+109
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-1/+1
* [mips] Rename functions. No functionality changes.Akira Hatanaka2013-05-131-2/+2
* [mips] Define overloaded versions of storeRegToStack and loadRegFromStack.Akira Hatanaka2013-03-291-10/+9
* Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters.Reed Kotler2013-02-251-55/+0
* Make psuedo FEXT_T8I816_ins into a custom emitter.Reed Kotler2013-02-241-53/+0
* Make psuedo FEXT_T8I816_ins a custom inserter. It should be expandedReed Kotler2013-02-241-22/+0
* Expand pseudos/macros:Reed Kotler2013-02-201-0/+56
* Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,Reed Kotler2013-02-191-1/+16
* Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.Reed Kotler2013-02-191-0/+26
* Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.Reed Kotler2013-02-181-0/+8
* Expand pseudo/macro BteqzT8SltuX16 . There is no test case becauseReed Kotler2013-02-181-0/+5
* Expand pseudo/macro BteqzT8SltX16.Reed Kotler2013-02-181-0/+3
* Expand macro/pseudo BteqzT8CmpX16.Reed Kotler2013-02-181-0/+3
* Beginning of expanding all current mips16 macro/pseudo instruction sequences.Reed Kotler2013-02-181-0/+15
* One more try to make this look nice. I have lots of pseudo lowering Reed Kotler2013-02-161-4/+9
* Use a different scheme to chose 16/32 variants. This scheme is moreReed Kotler2013-02-161-8/+6
* For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler2013-02-131-3/+12
* When Mips16 frames grow large, the immediate field may exceed the maximumReed Kotler2013-02-081-3/+72
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-191-19/+33
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