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path: root/llvm/lib/Target/MSP430/MSP430InstrInfo.h
Commit message (Expand)AuthorAgeFilesLines
* Use MCRegister in copyPhysRegMatt Arsenault2019-11-111-1/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [MSP430] Add MC layerAnton Korobeynikov2018-11-151-16/+0
* Revert "[MSP430] Add MC layer"Davide Italiano2018-11-081-0/+16
* [MSP430] Add MC layerAnton Korobeynikov2018-11-081-16/+0
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
* Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov2017-05-091-0/+6
* Finish renaming remaining analyzeBranch functionsMatt Arsenault2016-09-141-2/+2
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-141-1/+1
* AArch64: Use TTI branch functions in branch relaxationMatt Arsenault2016-09-141-2/+4
* TargetInstrInfo: add virtual function getInstSizeInBytesSjoerd Meijer2016-07-291-1/+1
* TargetInstrInfo: rename GetInstSizeInBytes to getInstSizeInBytes. NFCSjoerd Meijer2016-07-281-1/+1
* Rename AnalyzeBranch* to analyzeBranch*.Jacques Pienaar2016-07-151-2/+2
* MSP430: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-081-1/+1
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-5/+3
* CodeGen: TII: Take MachineInstr& in predicate API, NFCDuncan P. N. Exon Smith2016-02-231-1/+1
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-2/+2
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-2/+2
* [CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC.Ahmed Bougacha2015-06-111-2/+1
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
* Remove uses and caches of the target machine and subtarget fromEric Christopher2014-06-271-2/+2
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final...Craig Topper2014-04-291-19/+20
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-191-0/+1
* Revert r194865 and r194874.Alexey Samsonov2013-11-181-1/+0
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-151-0/+1
* Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer2012-06-061-1/+0
* Reorder includes in Target backends to following coding standards. Remove som...Craig Topper2012-03-171-1/+1
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-181-1/+1
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-011-1/+4
* Move callee-saved regs spills / reloads to TFIAnton Korobeynikov2010-11-271-9/+0
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-161-4/+0
* Replace copyRegToReg with copyPhysReg for MSP430.Jakob Stoklund Olesen2010-07-111-5/+4
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-171-1/+2
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-221-2/+4
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-1/+2
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-061-2/+4
* Add branch relaxation pass (shamelessly stolen from PPC).Anton Korobeynikov2010-01-151-0/+18
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-051-1/+0
* Implement branch foldingAnton Korobeynikov2009-10-211-3/+13
* Cosmetic changes, no functionality changesAnton Korobeynikov2009-10-211-14/+0
* Add InsertBranch() hook for tail mergeingAnton Korobeynikov2009-05-031-0/+4
* Lower select with custom inserted and make condjumps genericAnton Korobeynikov2009-05-031-2/+1
* Add first draft for conditions, conditional branches, etcAnton Korobeynikov2009-05-031-0/+15
* Add code for save/restore of callee-saved registersAnton Korobeynikov2009-05-031-1/+10
* First draft of stack slot loads / stores loweringAnton Korobeynikov2009-05-031-0/+9
* Add code enough for emission of reg-reg and reg-imm moves. This allows us to ...Anton Korobeynikov2009-05-031-0/+9
* Dummy MSP430 backendAnton Korobeynikov2009-05-031-0/+39
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