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* [MC] Thread unique_ptr<MCObjectWriter> through the create.*ObjectWriterLang Hames2017-10-103-6/+9
| | | | | | | | | | functions. This makes the ownership of the resulting MCObjectWriter clear, and allows us to remove one instance of MCObjectStreamer's bizarre "holding ownership via someone else's reference" trick. llvm-svn: 315327
* [MC] Plumb unique_ptr<MCELFObjectTargetWriter> through createELFObjectWriter toLang Hames2017-10-091-2/+2
| | | | | | | | | | ELFObjectWriter's constructor. Fixes the same ownership issue for ELF that r315245 did for MachO: ELFObjectWriter takes ownership of its MCELFObjectTargetWriter, so we want to pass this through to the constructor via a unique_ptr, rather than a raw ptr. llvm-svn: 315254
* Remove unused variables. No functionality change.Benjamin Kramer2017-10-082-2/+0
| | | | llvm-svn: 315185
* [Hexagon] Make PS_fi and PS_fia extendable (they both expand to A2_addi)Krzysztof Parzyszek2017-10-051-3/+6
| | | | llvm-svn: 315019
* [Hexagon] Give uniform names to functions changing addressing modes, NFCKrzysztof Parzyszek2017-10-054-56/+81
| | | | | | | | | | | | | | | The new format is changeAddrMode_xx_yy, where xx is the current mode, and yy is the new one. Old name: New name: getBaseWithImmOffset changeAddrMode_abs_io getAbsoluteForm changeAddrMode_io_abs getBaseWithRegOffset changeAddrMode_io_rr xformRegToImmOffset changeAddrMode_rr_io getBaseWithLongOffset changeAddrMode_rr_ur getRegShlForm changeAddrMode_ur_rr llvm-svn: 315013
* [RDF] Simplify construction of maximal registersKrzysztof Parzyszek2017-10-052-40/+12
| | | | | | | | The old algoritm was not correct, although it worked most of the time. Avoid the complex reachability analysis and simply calculate the maximal registers out of the set of all referenced registers. llvm-svn: 314991
* [Hexagon] Add a member Subtarget to HexagonInstrInfo, NFCKrzysztof Parzyszek2017-10-042-51/+25
| | | | llvm-svn: 314920
* [Hexagon] Check vector elements for equivalence in the ↵Ron Lieberman2017-10-021-1/+16
| | | | | | | | | | | | | HexagonVectorLoopCarriedReuse pass If the two instructions being compared for equivalence have corresponding operands that are integer constants, then check their values to determine equivalence. Patch by Suyog Sarda! llvm-svn: 314642
* [Hexagon] Patch to Extract i1 element from vector of i1Ron Lieberman2017-10-021-1/+7
| | | | | | | This patch extracts 1 element from vector consisting of elements of size 1 bit at given index. llvm-svn: 314641
* [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-09-2814-313/+398
| | | | | | other minor fixes (NFC). llvm-svn: 314467
* Reverted r313993.Galina Kistanova2017-09-271-15/+0
| | | | | | This patch produces a crash and hexagon_vector_loop_carried_reuse_constant.ll test fails on Windows (llvm-clang-x86_64-expensive-checks-win build bot). llvm-svn: 314361
* [Hexagon] Fix a typo: #ifndef DEBUG -> #ifndef NDEBUGKrzysztof Parzyszek2017-09-261-1/+1
| | | | llvm-svn: 314216
* [Hexagon] Fix initialization of HexagonSubtargetKrzysztof Parzyszek2017-09-262-38/+18
| | | | | | | Make sure that "initializeSubtargetDependencies" sets all members that InstrInfo and the like may depend on. llvm-svn: 314214
* [Hexagon] Avoid unused variable warnings in Release builds.Benjamin Kramer2017-09-251-2/+4
| | | | | | No functionality change intended. llvm-svn: 314143
* [Hexagon] Better determination of register classes in bit trackerKrzysztof Parzyszek2017-09-254-16/+68
| | | | | | | | | | | Add two callbacks to MachineEvaluator, so that specific implementations can specify more details about register classes: - composeWithSubRegIndex(RC,Idx), to provide the register class for a register from RC used in conjunction with a subregister index Idx. - getPhysRegBitWidth(Reg), to provide the size in bits of the given physical register. llvm-svn: 314136
* [Hexagon] Make getHexagonSubRegIndex take reference instead of pointerKrzysztof Parzyszek2017-09-255-16/+17
| | | | llvm-svn: 314134
* Check vector elements for equivalence in the HexagonVectorLoopCarriedReuse passPranav Bhandarkar2017-09-221-0/+15
| | | | | | | | | If the two instructions being compared for equivalence have corresponding operands that are integer constants, then check their values to determine equivalence. Patch by Suyog Sarda! llvm-svn: 313993
* HexagonVectorLoopCarriedReuse.cpp: Apply LLVM_ATTRIBUTE_UNUSED. ↵NAKAMURA Takumi2017-09-221-0/+2
| | | | | | [-Wunused-function] llvm-svn: 313947
* Reformat.NAKAMURA Takumi2017-09-221-2/+2
| | | | llvm-svn: 313946
* Fix unused variable warning.Richard Trieu2017-09-211-2/+1
| | | | | | | Move function call into debug macro to suppress unused variable warning in non-debug builds. llvm-svn: 313942
* Enable the reuse of values computed in a previous loop iteration.Pranav Bhandarkar2017-09-213-0/+588
| | | | | | | | | | This patch adds a pass that removes the computation of provably redundant expressions that have been computed earlier in a previous iteration. It relies on the use of PHIs to identify loop carried dependences. This is scalar replacement for vector types. llvm-svn: 313925
* [llvm] Fix some typos. NFC.Mandeep Singh Grang2017-09-151-1/+1
| | | | | | | | | | | | Reviewers: mcrosier Reviewed By: mcrosier Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D37922 llvm-svn: 313388
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-1529-13785/+2407
| | | | | | | This removes the duplicate HVX instruction set for the 128-byte mode. Single instruction set now works for both modes (64- and 128-byte). llvm-svn: 313362
* [Hexagon] Make getMemAccessSize return size in bytesKrzysztof Parzyszek2017-09-147-58/+65
| | | | | | | | It used to return the actual field value from the instruction descriptor. There is no reason for that, that value is not interesting in any way and the specifics of its encoding in the descriptor should not be exposed. llvm-svn: 313257
* [Hexagon] Add option to generate calls to "abort" for "unreachable"Krzysztof Parzyszek2017-09-061-0/+6
| | | | llvm-svn: 312644
* [Hexagon] Check for potential bank conflicts in post-RA schedulingKrzysztof Parzyszek2017-08-283-0/+55
| | | | | | | Insert artificial edges between loads that could cause a cache bank conflict. llvm-svn: 311901
* [Hexagon] Break up DAG mutations into separate classes, move to subtargetKrzysztof Parzyszek2017-08-286-139/+141
| | | | llvm-svn: 311895
* [Hexagon] Move pre-RA DAG mutations to scheduler constructorKrzysztof Parzyszek2017-08-283-15/+15
| | | | llvm-svn: 311894
* [Hexagon] Set access size for vector pseudo loads/storesKrzysztof Parzyszek2017-08-241-26/+26
| | | | llvm-svn: 311690
* [Hexagon] Generate correct runtime check when recognizing memmoveKrzysztof Parzyszek2017-08-241-3/+4
| | | | | | | | | | | | | | The check (assuming positive stride) for validity of memmove should be (a) the destination is at a lower address than the source, or (b) the distance between the source and destination is greater than or equal the number of bytes copied. For the second part it is sufficient to assume that the destination is at a higher address, since the opposite case is covered by (a). The distance calculation was previously done by subtracting the pointers in the wrong order. llvm-svn: 311650
* Add "Restored" flag to CalleeSavedInfoKrzysztof Parzyszek2017-08-101-1/+1
| | | | | | | | | | | The liveness-tracking code assumes that the registers that were saved in the function's prolog are live outside of the function. Specifically, that registers that were saved are also live-on-exit from the function. This isn't always the case as illustrated by the LR register on ARM. Differential Revision: https://reviews.llvm.org/D36160 llvm-svn: 310619
* [Hexagon] Use isMetaInstruction instead of isDebugValueKrzysztof Parzyszek2017-08-103-3/+4
| | | | llvm-svn: 310601
* [Hexagon] Ignore DBG_VALUEs when counting instructions in hexagon-early-ifKrzysztof Parzyszek2017-08-092-5/+8
| | | | llvm-svn: 310524
* [Hexagon] Tie implicit uses to defs in predicated instructionsKrzysztof Parzyszek2017-08-091-6/+22
| | | | llvm-svn: 310514
* Delete Default and JITDefault code modelsRafael Espindola2017-08-032-9/+16
| | | | | | | | | | | | | | | IMHO it is an antipattern to have a enum value that is Default. At any given piece of code it is not clear if we have to handle Default or if has already been mapped to a concrete value. In this case in particular, only the target can do the mapping and it is nice to make sure it is always done. This deletes the two default enum values of CodeModel and uses an explicit Optional<CodeModel> when it is possible that it is unspecified. llvm-svn: 309911
* Remove unused includes of MachineLocation.h (NFC)Adrian Prantl2017-08-021-1/+0
| | | | llvm-svn: 309824
* [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-08-0125-398/+562
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309746
* [Hexagon] Convert HVX vector constants of i1 to i8Krzysztof Parzyszek2017-08-011-0/+36
| | | | | | | | | Certain operations require vector of i1 values. However, for Hexagon architecture compatibility, they need to be represented as vector of i8. Patch by Suyog Sarda. llvm-svn: 309677
* Exclude more unused functions from release build.Florian Hahn2017-07-311-0/+4
| | | | llvm-svn: 309576
* Guard print() functions only used by dump() functions.Florian Hahn2017-07-311-0/+2
| | | | | | | | | | | | | | | | | | | Summary: Since r293359, most dump() function are only defined when `!defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)` holds. print() functions only used by dump() functions are now unused in release builds, generating lots of warnings. This patch only defines some print() functions if they are used. Reviewers: MatzeB Reviewed By: MatzeB Subscribers: arsenm, mzolotukhin, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D35949 llvm-svn: 309553
* [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-07-298-216/+279
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309469
* [Hexagon] Formatting changes, NFCKrzysztof Parzyszek2017-07-281-66/+49
| | | | llvm-svn: 309442
* [Hexagon] Fix expensive checks build bot broken in r309230.Eugene Zelenko2017-07-261-0/+1
| | | | llvm-svn: 309236
* [Hexagon] Partially revert r309230 which caused some build bots failures.Eugene Zelenko2017-07-261-9/+7
| | | | llvm-svn: 309233
* [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-07-2614-179/+237
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309230
* [Hexagon] Mark raise_relocation_error as NORETURN.Florian Hahn2017-07-261-0/+1
| | | | | | | | | | | | | | | | Summary: This silences a couple of implicit fallthrough warnings with GCC 7.1 in this file. Reviewers: colinl, kparzysz Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35889 llvm-svn: 309129
* TargetLowering: Change isShuffleMaskLegal's mask argument type to ↵Zvi Rackover2017-07-262-4/+3
| | | | | | | | | | | | | ArrayRef<int>. NFCI. Changing mask argument type from const SmallVectorImpl<int>& to ArrayRef<int>. This came up in D35700 where a mask is received as an ArrayRef<int> and we want to pass it to TargetLowering::isShuffleMaskLegal(). Also saves a few lines of code. llvm-svn: 309085
* [Hexagon] Recognize C4_cmpneqi, C4_cmpltei and C4_cmplteui in NewValueJumpKrzysztof Parzyszek2017-07-241-1/+25
| | | | llvm-svn: 308914
* [Hexagon] Add inline-asm constraint 'a' for modifier register classKrzysztof Parzyszek2017-07-211-2/+10
| | | | | | | For example asm ("memw(%0++%1) = %2" : : "r"(addr),"a"(mod),"r"(val) : "memory") llvm-svn: 308761
* [SystemZ, LoopStrengthReduce]Jonas Paulsson2017-07-212-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes LSR generate better code for SystemZ in the cases of memory intrinsics, Load->Store pairs or comparison of immediate with memory. In order to achieve this, the following common code changes were made: * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if LSR should do instruction-based addressing evaluations by calling isLegalAddressingMode() with the Instruction pointers. * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address, not just loads or stores. SystemZ changes: * isLSRCostLess() implemented with Insns first, and without ImmCost. * New function supportedAddressingMode() that is a helper for TTI methods looking at Instructions passed via pointers. Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D35262 https://reviews.llvm.org/D35049 llvm-svn: 308729
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