| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [SelectionDAG] Allow targets to specify legality of extloads' result | Ahmed Bougacha | 2015-01-08 | 1 | -2/+4 |
| * | [Hexagon] Fix 225372 USR register is not fully complete. Removing Uses = [US... | Colin LeMahieu | 2015-01-07 | 1 | -12/+12 |
| * | [Hexagon] Adding floating point classification and creation. | Colin LeMahieu | 2015-01-07 | 1 | -0/+45 |
| * | [Hexagon] Adding encodings for v5 floating point instructions. | Colin LeMahieu | 2015-01-07 | 1 | -0/+326 |
| * | [Hexagon] Adding encoding for popcount, fastcorner, dword asr with rounding. | Colin LeMahieu | 2015-01-07 | 2 | -1/+62 |
| * | [Hexagon] Adding compound jump encodings. | Colin LeMahieu | 2015-01-06 | 2 | -0/+266 |
| * | [Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dc... | Colin LeMahieu | 2015-01-06 | 3 | -1/+101 |
| * | [Hexagon] Adding encoding information for absolute address loads. | Colin LeMahieu | 2015-01-06 | 1 | -124/+186 |
| * | [Hexagon] Fix 225267. GP register is not yet fully implemented. Removing Us... | Colin LeMahieu | 2015-01-06 | 1 | -2/+2 |
| * | [Hexagon] Adding dealloc_return encoding and absolute address stores. | Colin LeMahieu | 2015-01-06 | 5 | -239/+347 |
| * | [Hexagon] Adding add/sub with carry, logical shift left by immediate and memo... | Colin LeMahieu | 2015-01-05 | 2 | -226/+124 |
| * | [Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accu... | Colin LeMahieu | 2015-01-05 | 1 | -57/+170 |
| * | [Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without ... | Colin LeMahieu | 2015-01-05 | 1 | -251/+104 |
| * | [Hexagon] Adding V4 logic-logic instructions and tests. | Colin LeMahieu | 2015-01-05 | 1 | -0/+55 |
| * | [Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions. | Colin LeMahieu | 2015-01-05 | 1 | -0/+57 |
| * | [Hexagon] Adding round reg/imm and bitsplit instructions. | Colin LeMahieu | 2015-01-05 | 2 | -0/+21 |
| * | Replace several 'assert(false' with 'llvm_unreachable' or fold a condition in... | Craig Topper | 2015-01-05 | 1 | -1/+1 |
| * | Reverting 225045 and 225043 and XFAIL multiline.ll on hexagon | Colin LeMahieu | 2014-12-31 | 1 | -1/+1 |
| * | [Hexagon] Removing assertion to appease buildbot until I can reproduce the pr... | Colin LeMahieu | 2014-12-31 | 1 | -1/+0 |
| * | [Hexagon] Changing an llvm_unreachable to an assertion and returning 0. Relo... | Colin LeMahieu | 2014-12-31 | 1 | -1/+2 |
| * | [Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doublew... | Colin LeMahieu | 2014-12-31 | 1 | -0/+111 |
| * | [Hexagon] Adding double-logic on predicate instructions. | Colin LeMahieu | 2014-12-30 | 1 | -0/+60 |
| * | [Hexagon] Adding newvalue compare and jumps. | Colin LeMahieu | 2014-12-30 | 1 | -17/+35 |
| * | [Hexagon] Adding postincrement register newvalue stores. | Colin LeMahieu | 2014-12-30 | 1 | -0/+30 |
| * | [Hexagon] Removing old newvalue store variants. Adding postincrement immedia... | Colin LeMahieu | 2014-12-30 | 2 | -96/+90 |
| * | [Hexagon] Adding indexed store new-value variants. | Colin LeMahieu | 2014-12-30 | 2 | -45/+100 |
| * | [Hexagon] Adding indexed store of immediates. | Colin LeMahieu | 2014-12-30 | 2 | -48/+97 |
| * | [Hexagon] Adding indexed stores. | Colin LeMahieu | 2014-12-30 | 2 | -81/+167 |
| * | [Hexagon] Adding reg-reg indexed load forms. | Colin LeMahieu | 2014-12-30 | 3 | -85/+135 |
| * | [Hexagon] Dropping old combine instructions without encodings. | Colin LeMahieu | 2014-12-30 | 3 | -79/+68 |
| * | [Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare... | Colin LeMahieu | 2014-12-30 | 1 | -55/+121 |
| * | [Hexagon] Updating constant extender def, adding alu-not instructions, compar... | Colin LeMahieu | 2014-12-30 | 2 | -10/+43 |
| * | [Hexagon] Adding allocframe, post-increment circular immediate stores, post-i... | Colin LeMahieu | 2014-12-29 | 3 | -17/+149 |
| * | [Hexagon] Fixing 224952 where an addressing mode update was missed. | Colin LeMahieu | 2014-12-29 | 1 | -1/+1 |
| * | [Hexagon] Adding post-increment register form stores and register-immediate f... | Colin LeMahieu | 2014-12-29 | 6 | -180/+194 |
| * | [Hexagon] Replacing the remaining postincrement stores with versions that hav... | Colin LeMahieu | 2014-12-29 | 3 | -58/+20 |
| * | [Hexagon] Renaming old multiclass for removal. Adding post-increment store c... | Colin LeMahieu | 2014-12-29 | 3 | -9/+104 |
| * | [Hexagon] Adding auto-incrementing loads with and without byte reversal. | Colin LeMahieu | 2014-12-26 | 1 | -0/+76 |
| * | [Hexagon] Adding locked loads. | Colin LeMahieu | 2014-12-26 | 1 | -0/+19 |
| * | [Hexagon] Adding deallocframe and circular addressing loads. | Colin LeMahieu | 2014-12-26 | 5 | -8/+124 |
| * | [Hexagon] Adding remaining post-increment instruction variants. Removing unu... | Colin LeMahieu | 2014-12-26 | 3 | -61/+25 |
| * | [Hexagon] Adding post-increment unsigned byte loads. | Colin LeMahieu | 2014-12-26 | 3 | -6/+5 |
| * | [Hexagon] Adding post-increment signed byte loads with tests. | Colin LeMahieu | 2014-12-26 | 3 | -12/+110 |
| * | [Hexagon] Removing old classes. | Colin LeMahieu | 2014-12-24 | 1 | -80/+0 |
| * | [Hexagon] Adding doubleword load. | Colin LeMahieu | 2014-12-23 | 4 | -29/+17 |
| * | [Hexagon] Reapplying 224775 load words. | Colin LeMahieu | 2014-12-23 | 7 | -46/+39 |
| * | Reverting 224775 until mayLoad flag is addressed. | Colin LeMahieu | 2014-12-23 | 6 | -38/+46 |
| * | [Hexagon] Adding word loads. | Colin LeMahieu | 2014-12-23 | 6 | -46/+38 |
| * | [Hexagon] Adding signed halfword loads. | Colin LeMahieu | 2014-12-23 | 5 | -30/+20 |
| * | [Hexagon] Adding unsigned halfword load. | Colin LeMahieu | 2014-12-23 | 5 | -20/+18 |
