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* [RDF] Further improve handling of multiple phis reached from shadowsKrzysztof Parzyszek2016-09-081-31/+16
| | | | llvm-svn: 280987
* [Hexagon] Expand sext- and zextloads of vector types, not just extloadsKrzysztof Parzyszek2016-09-081-1/+5
| | | | | | Recent change exposed this issue, breaking the Hexagon buildbots. llvm-svn: 280973
* [RDF] Fix liveness analysis for phi nodes with shadow usesKrzysztof Parzyszek2016-09-072-37/+82
| | | | | | | | Shadow uses need to be analyzed together, since each individual shadow will only have a partial reaching def. All shadows together may cover a given register ref, while each individual shadow may not. llvm-svn: 280855
* [RDF] Introduce "undef" flag for ref nodesKrzysztof Parzyszek2016-09-073-24/+74
| | | | llvm-svn: 280851
* [RDF] Ignore undef use operandsKrzysztof Parzyszek2016-09-061-1/+1
| | | | llvm-svn: 280717
* Make sure to maintain register liveness when generating predicated instructions.Ron Lieberman2016-09-021-22/+56
| | | | | | | | Author: Krzysztof Parzyszek <kparzysz@codeaurora.org> Differential Revision: https://reviews.llvm.org/D24209 llvm-svn: 280552
* [Hexagon] Deal with undefs when extending live intervalsKrzysztof Parzyszek2016-09-011-1/+1
| | | | | | Reapply r280275, since MSVC accepts r280358. llvm-svn: 280369
* [NFC] Remove unnecessary commentDean Michael Berris2016-09-011-4/+2
| | | | llvm-svn: 280336
* [XRay][NFC] Promote isTailCall() as virtual in TargetInstrInfo.Dean Michael Berris2016-09-011-1/+4
| | | | | | | This change is broken out from D23986, where XRay detects tail call exits. llvm-svn: 280331
* Revert "Add an optional parameter with a list of undefs to extendToIndices"Reid Kleckner2016-08-311-1/+1
| | | | | | | | | | | | This reverts commit r280268, it causes all MSVC 2013 to ICE. This appears to have been fixed in a later MSVC 2013 update, because I cannot reproduce it locally. That said, all upstream LLVM bots are broken right now, so I am reverting. Also reverts dependent change r280275, "[Hexagon] Deal with undefs when extending live intervals". llvm-svn: 280301
* [Hexagon] Deal with undefs when extending live intervalsKrzysztof Parzyszek2016-08-311-1/+1
| | | | llvm-svn: 280275
* [Hexagon] Remove extraneous debug output from HexagonCopyToCombine.cpp Ron Lieberman2016-08-251-1/+0
| | | | | | BB# ... llvm-svn: 279750
* [Hexagon] vector store print tracing.Ron Lieberman2016-08-251-4/+14
| | | | | | | | Add vector store print tracing option for hexagon vector instructions. https://reviews.llvm.org/D23870 llvm-svn: 279739
* MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, ↵Matthias Braun2016-08-259-9/+9
| | | | | | | | | | | | | compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
* [Hexagon] Check for block end when skipping debug instructionsKrzysztof Parzyszek2016-08-241-4/+3
| | | | llvm-svn: 279681
* [Hexagon] Change insertion of expand-condsets pass to avoid memory leaksKrzysztof Parzyszek2016-08-242-5/+10
| | | | llvm-svn: 279678
* [Hexagon] Enable subregister liveness trackingKrzysztof Parzyszek2016-08-241-1/+1
| | | | llvm-svn: 279642
* [Hexagon] Remove the utilization of IMPLICIT_DEFs from expand-condsetsKrzysztof Parzyszek2016-08-241-104/+1
| | | | | | | This is no longer necessary, because since r279625 the subregister liveness properly accounts for read-undefs. llvm-svn: 279637
* Create subranges for new intervals resulting from live interval splittingKrzysztof Parzyszek2016-08-241-1/+7
| | | | | | | | | | | | | | | | | | | The register allocator can split a live interval of a register into a set of smaller intervals. After the allocation of registers is complete, the rewriter will modify the IR to replace virtual registers with the corres- ponding physical registers. At this stage, if a register corresponding to a subregister of a virtual register is used, the rewriter will check if that subregister is undefined, and if so, it will add the <undef> flag to the machine operand. The function verifying liveness of the subregis- ter would assume that it is undefined, unless any of the subranges of the live interval proves otherwise. The problem is that the live intervals created during splitting do not have any subranges, even if the original parent interval did. This could result in the <undef> flag placed on a register that is actually defined. Differential Revision: http://reviews.llvm.org/D21189 llvm-svn: 279625
* CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePassesMatthias Braun2016-08-245-8/+0
| | | | | | | | | | | | | | | | | | | | | | Re-apply this patch, hopefully I will get away without any warnings in the constructor now. This patch removes the MachineFunctionAnalysis. Instead we keep a map from IR Function to MachineFunction in the MachineModuleInfo. This allows the insertion of ModulePasses into the codegen pipeline without breaking it because the MachineFunctionAnalysis gets dropped before a module pass. Peak memory should stay unchanged without a ModulePass in the codegen pipeline: Previously the MachineFunction was freed at the end of a codegen function pipeline because the MachineFunctionAnalysis was dropped; With this patch the MachineFunction is freed after the AsmPrinter has finished. Differential Revision: http://reviews.llvm.org/D23736 llvm-svn: 279602
* Revert r279564. It introduces undefined behavior (binding a reference to aRichard Smith2016-08-235-0/+8
| | | | | | | dereferenced null pointer) in MachineModuleInfo::MachineModuleInfo that causes -Werror builds (including several buildbots) to fail. llvm-svn: 279580
* CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePassesMatthias Braun2016-08-235-8/+0
| | | | | | | | | | | | | | | | | | | | | | | Re-apply this commit with the deletion of a MachineFunction delegated to a separate pass to avoid use after free when doing this directly in AsmPrinter. This patch removes the MachineFunctionAnalysis. Instead we keep a map from IR Function to MachineFunction in the MachineModuleInfo. This allows the insertion of ModulePasses into the codegen pipeline without breaking it because the MachineFunctionAnalysis gets dropped before a module pass. Peak memory should stay unchanged without a ModulePass in the codegen pipeline: Previously the MachineFunction was freed at the end of a codegen function pipeline because the MachineFunctionAnalysis was dropped; With this patch the MachineFunction is freed after the AsmPrinter has finished. Differential Revision: http://reviews.llvm.org/D23736 llvm-svn: 279564
* [Hexagon] Packetize return value setup with the return instructionKrzysztof Parzyszek2016-08-231-3/+4
| | | | | | Commit r279241 unintentionally reverted that ability. llvm-svn: 279526
* Revert "(HEAD -> master, origin/master, origin/HEAD) CodeGen: Remove ↵Matthias Braun2016-08-235-0/+8
| | | | | | | | | | MachineFunctionAnalysis => Enable (Machine)ModulePasses" Reverting while tracking down a use after free. This reverts commit r279502. llvm-svn: 279503
* CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePassesMatthias Braun2016-08-235-8/+0
| | | | | | | | | | | | | | | | | | | This patch removes the MachineFunctionAnalysis. Instead we keep a map from IR Function to MachineFunction in the MachineModuleInfo. This allows the insertion of ModulePasses into the codegen pipeline without breaking it because the MachineFunctionAnalysis gets dropped before a module pass. Peak memory should stay unchanged without a ModulePass in the codegen pipeline: Previously the MachineFunction was freed at the end of a codegen function pipeline because the MachineFunctionAnalysis was dropped; With this patch the MachineFunction is freed after the AsmPrinter has finished. Differential Revision: http://reviews.llvm.org/D23736 llvm-svn: 279502
* [Hexagon] Avoid register dependencies on indirect branches in packetizerKrzysztof Parzyszek2016-08-191-7/+8
| | | | | | | Do not packetize the instruction setting the branch address with the indirect branch itself. llvm-svn: 279324
* [Hexagon] Fix subesthetic indentationKrzysztof Parzyszek2016-08-193-51/+50
| | | | llvm-svn: 279303
* [Hexagon] Allow i1 values for 'r' constraint in inline-asmKrzysztof Parzyszek2016-08-191-2/+3
| | | | llvm-svn: 279302
* [Hexagon] Do not cache alloca instructions during iselKrzysztof Parzyszek2016-08-195-29/+6
| | | | | | | | They can be deleted or replicated, so the cache may become outdated. They only need to be visited once during frame lowering, so just scan the function instead. llvm-svn: 279297
* [Hexagon] Fixes for new-value jump formationKrzysztof Parzyszek2016-08-191-10/+31
| | | | | | | - Recognize C2_cmpgtui, S2_tstbit_i, and S4_ntstbit_i. - Avoid creating new-value instructions with both source operands equal. llvm-svn: 279286
* [Hexagon] Fix a few omissions in HexagonInstrInfoKrzysztof Parzyszek2016-08-191-0/+3
| | | | llvm-svn: 279280
* [Hexagon] Enforce LLSC packetization rulesKrzysztof Parzyszek2016-08-191-0/+18
| | | | | | | | | Ensure that load locked and store conditional instructions are only packetized with ALU32 instructions. Patch by Ben Craig. llvm-svn: 279272
* [Hexagon] Minor updates to register definitionsKrzysztof Parzyszek2016-08-191-4/+5
| | | | llvm-svn: 279269
* [Hexagon] Fix incorrect generation of S4_subi_asl_riKrzysztof Parzyszek2016-08-191-14/+29
| | | | | | Patch by Jyotsna Verma. llvm-svn: 279267
* [Hexagon] Add missing pattern for C4_cmplteKrzysztof Parzyszek2016-08-191-0/+2
| | | | llvm-svn: 279265
* [Hexagon] Make p0 an explicit operand in VA1_clr* subinstructions, NFCKrzysztof Parzyszek2016-08-192-10/+15
| | | | llvm-svn: 279255
* [Hexagon] Add explicit default constructor for HexagonSelectionDAGInfoKrzysztof Parzyszek2016-08-191-0/+2
| | | | llvm-svn: 279254
* [Hexagon] Allow tail-call optimization when mixing C and fast calling convKrzysztof Parzyszek2016-08-191-3/+9
| | | | | | Patch by Arnold Schwaighofer. llvm-svn: 279251
* [Hexagon] Check for empty live intervalKrzysztof Parzyszek2016-08-191-0/+2
| | | | | | Patch by Brendon Cahoon. llvm-svn: 279249
* [Hexagon] Consider zext/sext of a load to i32 to be freeKrzysztof Parzyszek2016-08-192-0/+27
| | | | llvm-svn: 279248
* [Hexagon] Handle J2_jumptpt and J2_jumpfpt instructionsKrzysztof Parzyszek2016-08-193-2/+16
| | | | llvm-svn: 279246
* [Hexagon] Fix indentation, NFCKrzysztof Parzyszek2016-08-191-3/+3
| | | | llvm-svn: 279245
* [Hexagon] Remove unnecessary llvm::, NFCKrzysztof Parzyszek2016-08-191-1/+1
| | | | llvm-svn: 279244
* [Hexagon] Rename the HEXAGON_MC namespace to Hexagon_MC, NFCKrzysztof Parzyszek2016-08-193-4/+4
| | | | llvm-svn: 279243
* [Hexagon] Mark PS_jumpret as pseudo-instruction, expand it into J2_jumprKrzysztof Parzyszek2016-08-194-23/+28
| | | | llvm-svn: 279241
* [Hexagon] Improvements to handling and generation of FP instructionsKrzysztof Parzyszek2016-08-194-17/+106
| | | | | | | | | Improved handling of fma, floating point min/max, additional load/store instructions for floating point types. Patch by Jyotsna Verma. llvm-svn: 279239
* [SelectionDAG] Rename fextend -> fpextend, fround -> fpround, frnd -> froundMichael Kuperstein2016-08-182-3/+3
| | | | | | | | | | The names of the tablegen defs now match the names of the ISD nodes. This makes the world a slightly saner place, as previously "fround" matched ISD::FP_ROUND and not ISD::FROUND. Differential Revision: https://reviews.llvm.org/D23597 llvm-svn: 279129
* [Hexagon] Create vcombine in HexagonCopyToCombineKrzysztof Parzyszek2016-08-181-18/+56
| | | | llvm-svn: 279067
* Replace a few more "fall through" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-172-1/+2
| | | | | | Follow up to r278902. I had missed "fall through", with a space. llvm-svn: 278970
* Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-172-3/+3
| | | | | | | This is a mechanical change of comments in switches like fallthrough, fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead. llvm-svn: 278902
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