diff options
| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-08-19 19:17:28 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-08-19 19:17:28 +0000 |
| commit | 505eb498bd78f560354b2f36d3b2ae77115d58ab (patch) | |
| tree | 3d6706cd239aed8a262c8deb3e6e0cef87eec9d3 /llvm/lib/Target/Hexagon | |
| parent | 054e7d2ec121c2a8893a611ed3cd0ac592e17afd (diff) | |
| download | bcm5719-llvm-505eb498bd78f560354b2f36d3b2ae77115d58ab.tar.gz bcm5719-llvm-505eb498bd78f560354b2f36d3b2ae77115d58ab.zip | |
[Hexagon] Allow i1 values for 'r' constraint in inline-asm
llvm-svn: 279302
Diffstat (limited to 'llvm/lib/Target/Hexagon')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 6ba9a31b316..218f5c3e554 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2987,9 +2987,10 @@ HexagonTargetLowering::getRegForInlineAsmConstraint( switch (VT.SimpleTy) { default: llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type"); - case MVT::i32: - case MVT::i16: + case MVT::i1: case MVT::i8: + case MVT::i16: + case MVT::i32: case MVT::f32: return std::make_pair(0U, &Hexagon::IntRegsRegClass); case MVT::i64: |
