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* Reorganize MachineScheduler interfaces and publish them in the header.Andrew Trick2012-09-112-510/+18
| | | | | | | | | | | | | | The Hexagon target decided to use a lot of functionality from the target-independent scheduler. That's fine, and other targets should be able to do the same. This reorg and API update makes that easy. For the record, ScheduleDAGMI was not meant to be subclassed. Instead, new scheduling algorithms should be able to implement MachineSchedStrategy and be done. But if need be, it's nice to be able to extend ScheduleDAGMI, so I also made that easier. The target scheduler is somewhat more apt to break that way though. llvm-svn: 163580
* Add "blocked" heuristic to the Hexagon MI scheduler.Sergei Larin2012-09-102-177/+269
| | | | | | Improve AQ instruction selection in the Hexagon MI scheduler. llvm-svn: 163523
* Fix alignment of .comm and .lcomm on mingw32.Benjamin Kramer2012-09-071-1/+1
| | | | | | | | For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't use the same setting for both. Fix this by reintroducing the LCOMM enum. I verified this against mingw's gcc. llvm-svn: 163420
* MC: Overhaul handling of .lcommBenjamin Kramer2012-09-071-1/+1
| | | | | | | | | | | | | - Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). llvm-svn: 163395
* LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access thePranav Bhandarkar2012-09-051-0/+35
| | | | | | | | | | | | | | | subreg_hireg of register pair Rp. * lib/Target/Hexagon/HexagonPeephole.cpp(PeepholeDoubleRegsMap): New DenseMap similar to PeepholeMap that additionally records subreg info too. (runOnMachineFunction): Record information in PeepholeDoubleRegsMap and copy propagate the high sub-reg of Rp0 in Rp1 = lsr(Rp0, #32) to the instruction Rx = COPY Rp1:logreg_subreg. * test/CodeGen/Hexagon/remove_lsr.ll: New test. llvm-svn: 163214
* Remove redundant semicolons to fix -pedantic-errors build.Richard Smith2012-09-051-2/+2
| | | | llvm-svn: 163190
* Porting Hexagon MI Scheduler to the new API.Sergei Larin2012-09-048-1/+1377
| | | | | | | Change current Hexagon MI scheduler to use new converging scheduler. Integrates DFA resource model into it. llvm-svn: 163137
* Rename hasVolatileMemoryRef() to hasOrderedMemoryRef().Jakob Stoklund Olesen2012-08-291-2/+2
| | | | | | | | Ordered memory operations are more constrained than volatile loads and stores because they must be ordered with respect to all other memory operations. llvm-svn: 162861
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-221-1/+1
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
* fix HexagonSubtarget parsing of -mv flagSebastian Pop2012-08-201-17/+16
| | | | llvm-svn: 162217
* [Hexagon] Don't mark callee saved registers as clobbered by a tail callArnold Schwaighofer2012-08-131-9/+3
| | | | | | | | | | This was causing unnecessary spills/restores of callee saved registers. Fixes PR13572. Patch by Pranav Bhandarkar! llvm-svn: 161778
* Don't use getNextOperandForReg().Jakob Stoklund Olesen2012-08-081-1/+4
| | | | | | | | | This way of using getNextOperandForReg() was unlikely to work as intended. We don't give any guarantees about the order of operands in the use-def chains, so looking only at operands following a given operand in the chain doesn't make sense. llvm-svn: 161542
* default to use -mv4 when no version of Hexagon has been specifiedSebastian Pop2012-07-191-1/+5
| | | | | | | | | This fixes a bunch of make check failures of the form: Unknown Architecture Version. UNREACHABLE executed at ../lib/Target/Hexagon/HexagonSubtarget.cpp:60! llvm-svn: 160518
* Remove tabs.Bill Wendling2012-07-191-85/+85
| | | | llvm-svn: 160483
* Remove tabs.Bill Wendling2012-07-191-4/+4
| | | | llvm-svn: 160477
* Remove variable_ops from call instructions in most targets.Jakob Stoklund Olesen2012-07-133-10/+10
| | | | | | | | Call instructions are no longer required to be variadic, and variable_ops should only be used for instructions that encode a variable number of arguments, like the ARM stm/ldm instructions. llvm-svn: 160189
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-073-9/+14
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
* Consistently use AnalysisID types in TargetPassConfig.Bob Wilson2012-07-021-1/+1
| | | | | | | This makes it possible to just use a zero value to represent "no pass", so the phony NoPassID global variable is no longer needed. llvm-svn: 159568
* Add all codegen passes to the PassManager via TargetPassConfig.Bob Wilson2012-07-021-10/+10
| | | | | | | | This is a preliminary step toward having TargetPassConfig be able to start and stop the compilation at specified passes for unit testing and debugging. No functionality change. llvm-svn: 159567
* There are a number of generic inline asm operand modifiers thatJack Carter2012-06-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | up to r158925 were handled as processor specific. Making them generic and putting tests for these modifiers in the CodeGen/Generic directory caused a number of targets to fail. This commit addresses that problem by having the targets call the generic routine for generic modifiers that they don't currently have explicit code for. For now only generic print operands 'c' and 'n' are supported.vi Affected files: test/CodeGen/Generic/asm-large-immediate.ll lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/NVPTX/NVPTXAsmPrinter.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Target/Hexagon/HexagonAsmPrinter.cpp lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/Sparc/SparcAsmPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp lib/Target/Mips/MipsAsmPrinter.cpp MSP430 isn't represented because it did not even run with the long existing 'c' modifier and it was not apparent what needs to be done to get it inline asm ready. Contributer: Jack Carter llvm-svn: 159203
* llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.NAKAMURA Takumi2012-06-241-0/+2
| | | | llvm-svn: 159112
* Revert r158679 - use case is unclear (and it increases the memory footprint).Hal Finkel2012-06-221-1/+1
| | | | | | | | | | Original commit message: Allow up to 64 functional units per processor itinerary. This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. llvm-svn: 159027
* Allow up to 64 functional units per processor itinerary.Hal Finkel2012-06-181-1/+1
| | | | | | | This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. llvm-svn: 158679
* *typo: Cyles changed to CyclesKay Tiong Khoo2012-06-132-2/+2
| | | | llvm-svn: 158404
* Silence a gcc-4.6 warning: GCC fails to understand that secondReg and cmpOp2 areDuncan Sands2012-06-091-1/+1
| | | | | | correlated, and thinks that cmpOp2 may be used uninitialized. llvm-svn: 158263
* misched: Added MultiIssueItineraries.Andrew Trick2012-06-053-5/+9
| | | | | | | | This allows a subtarget to explicitly specify the issue width and other properties without providing pipeline stage details for every instruction. llvm-svn: 157979
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-026-8/+8
| | | | llvm-svn: 157885
* Switch some getAliasSet clients to MCRegAliasIterator.Jakob Stoklund Olesen2012-06-011-5/+2
| | | | | | | MCRegAliasIterator can optionally visit the register itself, allowing for simpler code. llvm-svn: 157837
* Extract some pointer hacking to a function.Jakob Stoklund Olesen2012-05-301-22/+22
| | | | | | Switch to MCSuperRegIterator while we're there. llvm-svn: 157717
* Fix some uses of getSubRegisters() to use getSubReg() instead.Jakob Stoklund Olesen2012-05-301-1/+1
| | | | | | | It is better to address sub-registers directly by name instead of relying on their position in the sub-register list. llvm-svn: 157703
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-252-14/+12
| | | | | | | | | | to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
* Hexagon: Remove unused command line option.Benjamin Kramer2012-05-161-2/+0
| | | | llvm-svn: 156917
* Revert 156634 upon request until code improvement changes are made.Brendon Cahoon2012-05-1415-3689/+339
| | | | llvm-svn: 156775
* Hexagon: Initialize TBB to 0.Benjamin Kramer2012-05-131-0/+1
| | | | | | Found by valgrind. llvm-svn: 156744
* Make sure new value jump is enabled for Hexagon V5 as well.Sirish Pande2012-05-121-10/+27
| | | | llvm-svn: 156700
* Support for Hexagon feature, New Value Jump.Sirish Pande2012-05-127-2/+682
| | | | llvm-svn: 156698
* Updated instruction table due to addded intrinsics.Brendon Cahoon2012-05-111-1880/+1943
| | | | llvm-svn: 156644
* Remove warnings from HexagonVLIWPacketizer.Sirish Pande2012-05-111-3/+3
| | | | llvm-svn: 156636
* Hexagon constant extender support.Brendon Cahoon2012-05-1115-339/+3626
| | | | | | Patch by Jyotsna Verma. llvm-svn: 156634
* Hexagon V5 intrinsics support.Sirish Pande2012-05-113-615/+1061
| | | | llvm-svn: 156631
* Hexagon V5 Support - V5 td file.Sirish Pande2012-05-101-0/+626
| | | | llvm-svn: 156569
* Hexagon V5 FP Support.Sirish Pande2012-05-1014-194/+519
| | | | llvm-svn: 156568
* Remove excess semi-colons to quiet warnings.Eric Christopher2012-05-081-6/+6
| | | | llvm-svn: 156416
* Update load/store instruction patterns in Hexagon V4.Sirish Pande2012-05-081-492/+492
| | | | llvm-svn: 156411
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-072-2/+2
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Remove the SubRegClasses field from RegisterClass descriptions.Jakob Stoklund Olesen2012-05-041-3/+1
| | | | | | This information in now computed by TableGen. llvm-svn: 156152
* Support for target dependent Hexagon VLIW packetizer.Sirish Pande2012-05-0314-93/+4967
| | | | | | This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
* Extensions of Hexagon V4 instructions.Sirish Pande2012-05-039-1339/+4107
| | | | | | This adds new instructions for Hexagon V4 architecture. llvm-svn: 156071
* Change the PassManager from a reference to a pointer.Bill Wendling2012-05-011-8/+8
| | | | | | | | | The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 llvm-svn: 155902
* This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd2012-04-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. llvm-svn: 155395
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