misched: Added MultiIssueItineraries.

This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.

llvm-svn: 157979

3 files changed, 9 insertions, 5 deletions

diff --git a/llvm/lib/Target/Hexagon/HexagonSchedule.td b/llvm/lib/Target/Hexagon/HexagonSchedule.td
index c4887963895..b4df6784e7d 100644
--- a/llvm/lib/Target/Hexagon/HexagonSchedule.td
+++ b/llvm/lib/Target/Hexagon/HexagonSchedule.td
@@ -41,7 +41,10 @@ def HexagonItineraries :
         InstrItinData<SYS    , [InstrStage<1, [LSUNIT]>]>,
         InstrItinData<MARKER , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
         InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>
-      ]>;
+      ]> {
+  // Max issue per cycle == bundle width.
+  let IssueWidth = 4;
+}
 
 //===----------------------------------------------------------------------===//
 // V4 Machine Info +
diff --git a/llvm/lib/Target/Hexagon/HexagonScheduleV4.td b/llvm/lib/Target/Hexagon/HexagonScheduleV4.td
index 1d82dbb90e9..8d6f7b2b7a9 100644
--- a/llvm/lib/Target/Hexagon/HexagonScheduleV4.td
+++ b/llvm/lib/Target/Hexagon/HexagonScheduleV4.td
@@ -52,7 +52,11 @@ def HexagonItinerariesV4 :
         InstrItinData<MARKER , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
         InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
         InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>
-      ]>;
+      ]> {
+  // Max issue per cycle == bundle width.
+  let IssueWidth = 4;
+}
+
 
 //===----------------------------------------------------------------------===//
 // Hexagon V4 Resource Definitions -
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index 8744b7b32c2..ce81a78bf94 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -61,9 +61,6 @@ HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS):
   // Initialize scheduling itinerary for the specified CPU.
   InstrItins = getInstrItineraryForCPU(CPUString);
 
-  // Max issue per cycle == bundle width.
-  InstrItins.IssueWidth = 4;
-
   if (EnableMemOps)
     UseMemOps = true;
   else