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* [SVE][MVT] Fixed-length vector MVT rangesGraham Hunter2019-09-171-1/+1
| | | | | | | | | | | | | | | | | * Reordered MVT simple types to group scalable vector types together. * New range functions in MachineValueType.h to only iterate over the fixed-length int/fp vector types. * Stopped backends which don't support scalable vector types from iterating over scalable types. Reviewers: sdesmalen, greened Reviewed By: greened Differential Revision: https://reviews.llvm.org/D66339 llvm-svn: 372099
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [Hexagon] Foundation of support for Hexagon V66Krzysztof Parzyszek2018-12-051-0/+8
| | | | llvm-svn: 348407
* [Hexagon] Implement noreturn optimizationBrendon Cahoon2018-11-091-0/+3
| | | | | | | | | | | Eliminate the stack frame in functions with the noreturn nounwind attributes, and when the noreturn-stack-elim target feature is enabled. This reduces the code and stack space needed for noreturn functions. Differential Revision: https://reviews.llvm.org/D54210 llvm-svn: 346532
* [Hexagon] Remove support for V4Krzysztof Parzyszek2018-10-191-2/+4
| | | | llvm-svn: 344791
* [Hexagon] Remove 'T' from HasVNN predicates, NFCKrzysztof Parzyszek2018-06-201-10/+10
| | | | | | Patch by Sumanth Gundapaneni. llvm-svn: 335124
* [Hexagon] Remove unused function from subtargetKrzysztof Parzyszek2018-05-151-8/+0
| | | | llvm-svn: 332369
* [Hexagon] Remove unused flag from subtarget and (non)corresponding testKrzysztof Parzyszek2018-05-151-2/+0
| | | | llvm-svn: 332365
* [Hexagon] Add a target feature to control using small data sectionKrzysztof Parzyszek2018-05-141-1/+4
| | | | llvm-svn: 332292
* [Hexagon] Add a target feature for generating new-value storesKrzysztof Parzyszek2018-05-141-0/+2
| | | | llvm-svn: 332290
* [Hexagon] Add a target feature for memop generationKrzysztof Parzyszek2018-05-141-6/+9
| | | | llvm-svn: 332285
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-2/+2
| | | | | | | | | | | | | | | | We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
* [Hexagon] Subtarget feature to emit one instruction per packetKrzysztof Parzyszek2018-03-121-0/+5
| | | | | | | | | | | | | | | | | This adds two features: "packets", and "nvj". Enabling "packets" allows the compiler to generate instruction packets, while disabling it will prevent it and disable all optimizations that generate them. This feature is enabled by default on all subtargets. The feature "nvj" allows the compiler to generate new-value jumps and it implies "packets". It is enabled on all subtargets. The exception is made for packets with endloop instructions, since they require a certain minimum number of instructions in the packets to which they apply. Disabling "packets" will not prevent hardware loops from being generated. llvm-svn: 327302
* [Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned onesKrzysztof Parzyszek2018-03-071-0/+6
| | | | | | | | | This is a follow-up to r325169, this time for all types, not just HVX vector types. Disable this by default, since it's not always safe. llvm-svn: 326915
* [Hexagon] Implement target feature +reserved-r19Krzysztof Parzyszek2018-02-281-0/+3
| | | | llvm-svn: 326364
* Attempt to pacify 4.8.5 with makeArrayRefReid Kleckner2017-12-211-1/+1
| | | | llvm-svn: 321233
* [Hexagon] Allow construction of HVX vector predicatesKrzysztof Parzyszek2017-12-201-4/+28
| | | | | | Handle BUILD_VECTOR of boolean values. llvm-svn: 321220
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-111-0/+9
| | | | llvm-svn: 320404
* [Hexagon] Implement HexagonSubtarget::useAA()Krzysztof Parzyszek2017-11-301-0/+5
| | | | llvm-svn: 319477
* [Hexagon] Implement HexagonSubtarget::isHVXVectorTypeKrzysztof Parzyszek2017-11-271-0/+10
| | | | llvm-svn: 319064
* [Hexagon] Add HexagonSubtarget::getVectorLength()Krzysztof Parzyszek2017-11-211-0/+9
| | | | llvm-svn: 318807
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* [Hexagon] New HVX target features.Sumanth Gundapaneni2017-10-181-4/+5
| | | | | | | | | | | | | | | | | | | | | | This patch lets the llvm tools handle the new HVX target features that are added by frontend (clang). The target-features are of the form "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX. "hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated. The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}. Eg: "+hvxv62" For the correct HVX code generation, the user must use the following target features. For 64B mode: "+hvxv62" "+hvx-length64b" For 128B mode: "+hvxv62" "+hvx-length128b" Clang picks a default length if none is specified. If for some reason, no hvx-length is specified to llvm, the compilation will bail out. There is a corresponding clang patch. Differential Revision: https://reviews.llvm.org/D38851 llvm-svn: 316101
* [Hexagon] Update Hexagon ArchEnum and sync some downstream changes(NFC)Sumanth Gundapaneni2017-10-181-13/+28
| | | | | | Differential Revision: https://reviews.llvm.org/D38850 llvm-svn: 316099
* [Hexagon] Fix initialization of HexagonSubtargetKrzysztof Parzyszek2017-09-261-2/+0
| | | | | | | Make sure that "initializeSubtargetDependencies" sets all members that InstrInfo and the like may depend on. llvm-svn: 314214
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-1/+3
| | | | | | | This removes the duplicate HVX instruction set for the 128-byte mode. Single instruction set now works for both modes (64- and 128-byte). llvm-svn: 313362
* [Hexagon] Check for potential bank conflicts in post-RA schedulingKrzysztof Parzyszek2017-08-281-0/+3
| | | | | | | Insert artificial edges between loads that could cause a cache bank conflict. llvm-svn: 311901
* [Hexagon] Break up DAG mutations into separate classes, move to subtargetKrzysztof Parzyszek2017-08-281-2/+10
| | | | llvm-svn: 311895
* [Target] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-06-191-4/+18
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 305757
* [Hexagon] Disable predicated calls by defaultKrzysztof Parzyszek2017-05-051-0/+1
| | | | llvm-svn: 302307
* [Hexagon] Use automatically-generated scheduling information for HVXKrzysztof Parzyszek2017-05-031-5/+4
| | | | | | Patch by Jyotsna Verma. llvm-svn: 302073
* [Hexagon] Introduce Hexagon V62Krzysztof Parzyszek2017-02-101-0/+3
| | | | llvm-svn: 294805
* [Hexagon] Replace instruction definitions with auto-generated onesKrzysztof Parzyszek2017-02-101-3/+1
| | | | llvm-svn: 294753
* [Hexagon] Add DAG mutations for machine pipelinerKrzysztof Parzyszek2016-12-221-0/+4
| | | | llvm-svn: 290366
* [Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFCKrzysztof Parzyszek2016-07-291-2/+2
| | | | llvm-svn: 277220
* [Hexagon] Add target feature to generate long callsKrzysztof Parzyszek2016-07-251-0/+2
| | | | llvm-svn: 276638
* [Hexagon] Use loop data prefetch on HexagonKrzysztof Parzyszek2016-07-221-0/+3
| | | | llvm-svn: 276422
* [Hexagon] Fix zero latency instructions with multiple predecessorsKrzysztof Parzyszek2016-07-181-2/+6
| | | | | | | | | | | An instruction may have multiple predecessors that are candidates for using .cur. However, only one of them can use .cur in the packet. When this case occurs, we need to make sure that only one of the dependences gets a 0 latency value. Patch by Brendon Cahoon. llvm-svn: 275790
* [Hexagon] Handle instruction latency for 0 or 2 cyclesKrzysztof Parzyszek2016-07-151-0/+10
| | | | | | | | | | | | | | | | | | | | | | | The Hexagon schedulers need to handle instructions with a latency of 0 or 2 more accurately. The problem, in v60, is that a dependence between two instructions with a 2 cycle latency can use a .cur version of the source to achieve a 0 cycle latency when the use is in the same packet. Any othe use, must be at least 2 packets later, or a stall occurs. In other words, the compiler does not want to schedule the dependent instructions 1 cycle later. To achieve this, the latency adjustment code allows only a single dependence to have a zero latency. All other instructions have the other value, which is typically 2 cycles. We use a heuristic to determine which instruction gets the 0 latency. The Hexagon machine scheduler was also changed to increase the cost associated with 0 latency dependences than can be scheduled in the same packet. Patch by Brendon Cahoon. llvm-svn: 275625
* [Hexagon] Add a scheduling DAG mutationKrzysztof Parzyszek2016-07-151-1/+9
| | | | | | | - Remove output dependencies on USR_OVF register. - Update chain edge latencies between v60 vector loads/stores. llvm-svn: 275586
* [Hexagon] Add option to enable subregister liveness trackingKrzysztof Parzyszek2016-05-281-0/+2
| | | | llvm-svn: 271088
* [Hexagon] Enable the post-RA schedulerKrzysztof Parzyszek2016-05-261-0/+1
| | | | | | | | | The aggressive anti-dependency breaker can rename the restored callee- saved registers. To prevent this, mark these registers are live on all paths to the return/tail-call instructions, and add implicit use operands for them to these instructions. llvm-svn: 270898
* [Hexagon] Select the aggressive anti-dependency breakerKrzysztof Parzyszek2016-05-261-0/+2
| | | | llvm-svn: 270857
* [Hexagon] Subtarget features/default CPU correctionsKrzysztof Parzyszek2015-12-141-1/+1
| | | | llvm-svn: 255501
* Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the defaultKrzysztof Parzyszek2015-11-251-1/+5
| | | | llvm-svn: 254089
* [Hexagon] Bring HexagonInstrInfo up to dateKrzysztof Parzyszek2015-11-241-0/+6
| | | | llvm-svn: 253986
* [Hexagon] Adding skeleton of HVX extension instructions.Colin LeMahieu2015-10-171-2/+6
| | | | llvm-svn: 250600
* Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and ↵Daniel Sanders2015-06-101-1/+1
| | | | | | | | | | | | | | | | | | create*MCSubtargetInfo(). NFC. Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: rafael Reviewed By: rafael Subscribers: rafael, ted, jfb, llvm-commits, rengolin, jholewinski Differential Revision: http://reviews.llvm.org/D10311 llvm-svn: 239467
* Remove useMachineScheduler and replace it with subtarget optionsEric Christopher2015-03-111-0/+5
| | | | | | | | | | | | | that control, individually, all of the disparate things it was controlling. At the same time move a FIXME in the Hexagon port to a new subtarget function that will enable a user of the machine scheduler to avoid using the source scheduler for pre-RA-scheduling. The FIXME would have this removed, but involves either testcase changes or adding -pre-RA-sched=source to a few testcases. llvm-svn: 231980
* [Hexagon] Removing more V4 predicates since V4 is the required minimum.Colin LeMahieu2015-02-091-13/+6
| | | | llvm-svn: 228614
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