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path: root/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
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* Revert "[Hexagon] Handle decreasing of stack alignment in frame lowering"Krzysztof Parzyszek2017-06-231-30/+0
* [Hexagon] Handle decreasing of stack alignment in frame loweringKrzysztof Parzyszek2017-06-231-0/+30
* [Hexagon] Cleanup of unused function isCalleeSaveReg (NFC)Sumanth Gundapaneni2017-05-261-5/+0
* [Hexagon] Implement @llvm.readcyclecounter()Krzysztof Parzyszek2017-02-221-2/+2
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-171-3/+9
* Revert "[Hexagon] Start using regmasks on calls"Rafael Espindola2017-02-171-9/+3
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-161-3/+9
* [Hexagon] Introduce Hexagon V62Krzysztof Parzyszek2017-02-101-11/+21
* [Hexagon] Explicitly reserve aliases of reserved registersKrzysztof Parzyszek2017-01-231-13/+20
* [Hexagon] Separate Hexagon subreg indices for different register classesKrzysztof Parzyszek2016-11-091-0/+22
* [Hexagon] Improvements to handling and generation of FP instructionsKrzysztof Parzyszek2016-08-191-0/+1
* [Hexagon] Standardize next batch of pseudo instructionsKrzysztof Parzyszek2016-08-161-2/+2
* Run clang-tidy's performance-unnecessary-copy-initialization over LLVM.Benjamin Kramer2016-06-121-1/+1
* [Hexagon] Make getCallerSavedRegs specific to a register classKrzysztof Parzyszek2016-05-161-14/+42
* [NFC] Header cleanupMehdi Amini2016-04-181-1/+0
* [Hexagon] Fix reserving emergency spill slots for register scavengerKrzysztof Parzyszek2016-03-211-2/+0
* [Hexagon] Implement TLS supportKrzysztof Parzyszek2016-02-181-0/+1
* [Hexagon] Update the callee-saved register set for EH-aware functionsKrzysztof Parzyszek2016-02-181-3/+15
* [Hexagon] Eliminate pseudo instructions for circ/brev loads and storesKrzysztof Parzyszek2016-02-121-1/+4
* [Hexagon] Handle out-of-range offsets in eliminateFrameIndexKrzysztof Parzyszek2016-02-121-12/+15
* [Hexagon] Mark D14 and GP as reserved registersKrzysztof Parzyszek2016-01-111-0/+2
* [Hexagon] Add PIC supportKrzysztof Parzyszek2015-12-181-1/+1
* [Hexagon] Fix debug information for local objectsKrzysztof Parzyszek2015-10-191-68/+13
* [Hexagon] Adding skeleton of HVX extension instructions.Colin LeMahieu2015-10-171-0/+4
* Targets: commonize some stack realignment codeJF Bastien2015-07-201-7/+0
* Target RegisterInfo: devirtualize TargetFrameLoweringJF Bastien2015-07-101-2/+3
* [Hexagon] Overhaul of stack object allocationKrzysztof Parzyszek2015-04-221-129/+142
* Remove unused complex patterns for addressing modes on Hexagon.Krzysztof Parzyszek2015-03-121-1/+3
* Remove subtarget dependence from HexagonRegisterInfo.Eric Christopher2015-03-101-7/+4
* [Hexagon] Removing more V4 predicates since V4 is the required minimum.Colin LeMahieu2015-02-091-50/+5
* [Hexagon] Renaming A2_addi and formatting.Colin LeMahieu2015-02-051-6/+6
* [Hexagon] Replacing old versions of stores and loads.Colin LeMahieu2015-01-151-5/+2
* [Hexagon] Replacing old version of convert and load f64.Colin LeMahieu2015-01-141-2/+1
* [Hexagon] Adding post-increment register form stores and register-immediate f...Colin LeMahieu2014-12-291-5/+4
* [Hexagon] Adding doubleword load.Colin LeMahieu2014-12-231-2/+2
* [Hexagon] Reapplying 224775 load words.Colin LeMahieu2014-12-231-1/+1
* Reverting 224775 until mayLoad flag is addressed.Colin LeMahieu2014-12-231-1/+1
* [Hexagon] Adding word loads.Colin LeMahieu2014-12-231-1/+1
* [Hexagon] Adding signed halfword loads.Colin LeMahieu2014-12-231-1/+1
* [Hexagon] Adding unsigned halfword load.Colin LeMahieu2014-12-231-1/+1
* [Hexagon] Adding memb instruction. Fixing whitespace in test from 224730.Colin LeMahieu2014-12-221-1/+1
* [Hexagon] Adding classes and load unsigned byte instruction, updating usages.Colin LeMahieu2014-12-221-1/+1
* [Hexagon] Converting from ADD_rr to A2_add which has encoding bits.Colin LeMahieu2014-11-181-4/+4
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-6/+3
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-3/+6
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-041-5/+4
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-071-5/+5
* Remove getEHExceptionRegister and getEHHandlerRegister.Rafael Espindola2013-10-071-8/+0
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-4/+4
* Remove unused function.Rafael Espindola2013-05-101-10/+0
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