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* [Hexagon] Add patterns for truncating HVX vector typesKrzysztof Parzyszek2018-01-051-0/+5
| | | | | | Only non-bool vectors. llvm-svn: 321895
* [Hexagon] Add patterns for sext_inreg of HVX vector typesKrzysztof Parzyszek2018-01-051-0/+19
| | | | llvm-svn: 321894
* [Hexagon] Add pattern for vsplat to v8i8Krzysztof Parzyszek2018-01-051-0/+5
| | | | llvm-svn: 321892
* [Hexagon] Replace INSERTRP/EXTRACTRP with INSERT/EXTRACT in HexagonISDKrzysztof Parzyszek2018-01-041-27/+21
| | | | llvm-svn: 321798
* [Hexagon] Fix generation of vector sign extensionsKrzysztof Parzyszek2018-01-021-17/+27
| | | | llvm-svn: 321650
* [Hexagon] Allow construction of HVX vector predicatesKrzysztof Parzyszek2017-12-201-0/+9
| | | | | | Handle BUILD_VECTOR of boolean values. llvm-svn: 321220
* [Hexagon] Generate HVX code for vector sign-, zero- and any-extendsKrzysztof Parzyszek2017-12-181-0/+25
| | | | | | Implement any-extend as zero-extend. llvm-svn: 321004
* [Hexagon] Handle concat_vectors of all allowed HVX typesKrzysztof Parzyszek2017-12-151-10/+17
| | | | llvm-svn: 320865
* [Hexagon] Fix operand-swapping PatFrag for atomic storesKrzysztof Parzyszek2017-12-151-18/+22
| | | | | | | PatFrag now has the atomicity information stored as bit fields. They need to be copied to the new PatFrag. llvm-svn: 320855
* [Hexagon] Generate HVX code for comparisons and selectsKrzysztof Parzyszek2017-12-141-3/+14
| | | | llvm-svn: 320744
* [Hexagon] Remove vectors of i64 from valid HVX typesKrzysztof Parzyszek2017-12-141-8/+0
| | | | | | HVX does not support operations on 64-bit integers. llvm-svn: 320722
* [Hexagon] Generate HVX code for basic arithmetic operationsKrzysztof Parzyszek2017-12-071-2/+12
| | | | | | Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32. llvm-svn: 320063
* [Hexagon] Generate HVX code for vector construction and accessKrzysztof Parzyszek2017-12-061-28/+68
| | | | | | | | | | Support for: - build vector, - extract vector element, subvector, - insert vector element, subvector, - shuffle. llvm-svn: 319901
* [Hexagon] Remove HexagonISD::PACKHLKrzysztof Parzyszek2017-11-291-4/+1
| | | | llvm-svn: 319352
* [Hexagon] Add patterns to select A2_combine_ll and its variantsKrzysztof Parzyszek2017-11-221-0/+10
| | | | llvm-svn: 318876
* [Hexagon] Prefer L2_loadrub_io over L4_loadrub_rrKrzysztof Parzyszek2017-11-021-52/+82
| | | | | | | If the offset is an immediate, avoid putting it in a register to get Rs+Rt<<#0. llvm-svn: 317275
* [Hexagon] Adjust patterns to reflect instruction selection preferencesKrzysztof Parzyszek2017-10-271-7/+30
| | | | llvm-svn: 316804
* [Hexagon] Add extra pattern for S4_addaddiKrzysztof Parzyszek2017-10-231-0/+2
| | | | | | One combination was missing: add(add(x,y),c). llvm-svn: 316363
* [Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek2017-10-201-2557/+2103
| | | | llvm-svn: 316228
* [Hexagon] Add patterns for cmpb/cmph with immediate argumentsKrzysztof Parzyszek2017-10-131-0/+46
| | | | | | Patch by Sumanth Gundapaneni. llvm-svn: 315692
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-199/+76
| | | | | | | This removes the duplicate HVX instruction set for the 128-byte mode. Single instruction set now works for both modes (64- and 128-byte). llvm-svn: 313362
* [Hexagon] Remove custom lowering of loads of v4i16Krzysztof Parzyszek2017-07-171-0/+6
| | | | | | | The target-independent lowering works fine, except concatenating 32-bit words. Add a pattern to generate A2_combinew instead of 64-bit asl/or. llvm-svn: 308186
* [Hexagon] Replace ISD opcode VPACK with VPACKE/VPACKO, NFCKrzysztof Parzyszek2017-07-141-39/+34
| | | | | | This breaks up pack-even and pack-odd into two separate operations. llvm-svn: 308049
* [Hexagon] Use VSPLAT instead of COMBINE for vectors of type v2i32, NFCKrzysztof Parzyszek2017-07-131-6/+7
| | | | | | This cleans up the vector shift patterns. llvm-svn: 307935
* [Hexagon] Add support for nontemporal loads and stores on HVXKrzysztof Parzyszek2017-07-111-0/+41
| | | | | | | | Patch by Michael Wu. Differential Revision: https://reviews.llvm.org/D35104 llvm-svn: 307671
* [Hexagon] Convert typed ISD opcodes to generic ones, NFCKrzysztof Parzyszek2017-07-101-31/+26
| | | | llvm-svn: 307582
* [Hexagon] Remove unused ISD opcodes, NFCKrzysztof Parzyszek2017-07-101-67/+0
| | | | llvm-svn: 307580
* [Hexagon] Generate store-immediate instructions for stack objectsKrzysztof Parzyszek2017-06-131-4/+10
| | | | | | | | | Store-immediate instructions have a non-extendable offset. Since the actual offset for a stack object is not known until much later, only generate these stores when the stack size (at the time of instruction selection) is small. llvm-svn: 305305
* [Hexagon] Generate multiply-high instruction in iselKrzysztof Parzyszek2017-06-131-0/+5
| | | | llvm-svn: 305302
* [Hexagon] Fixes and updates to the selection patternsKrzysztof Parzyszek2017-06-091-28/+52
| | | | | | | | - Add some missing patterns. - Use C4_cmplte in branch patterns. - Fix signedness of immediate operand in M2_accii. llvm-svn: 305085
* [Hexagon] Add LLVM header to HexagonPatterns.tdKrzysztof Parzyszek2017-06-091-0/+9
| | | | llvm-svn: 305074
* [Hexagon] Improve code generation for 32x32-bit multiplicationKrzysztof Parzyszek2017-05-301-32/+27
| | | | | | | | | For multiplications of 64-bit values (giving 64-bit result), detect cases where the arguments are sign-extended 32-bit values, on a per- operand basis. This will allow few patterns to match a wider variety of combinations in which extensions can occur. llvm-svn: 304223
* Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov2017-05-091-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 llvm-svn: 302527
* [Hexagon] Use automatically-generated scheduling information for HVXKrzysztof Parzyszek2017-05-031-8/+0
| | | | | | Patch by Jyotsna Verma. llvm-svn: 302073
* [Hexagon] Change the vector scaling for vector offsetsKrzysztof Parzyszek2017-04-061-16/+26
| | | | | | | Keep full offset value on MI-level instructions, but have it scaled down in the MC-level instructions. llvm-svn: 299664
* [Hexagon] Fix instruction selection for sign-extending i1 to i64Krzysztof Parzyszek2017-02-281-27/+28
| | | | llvm-svn: 296532
* [Hexagon] Patterns for CTPOP, BSWAP and BITREVERSEKrzysztof Parzyszek2017-02-231-6/+9
| | | | llvm-svn: 295981
* [Hexagon] Implement @llvm.readcyclecounter()Krzysztof Parzyszek2017-02-221-0/+8
| | | | llvm-svn: 295892
* [Hexagon] Replace instruction definitions with auto-generated onesKrzysztof Parzyszek2017-02-101-17/+10
| | | | llvm-svn: 294753
* [Hexagon] Give a predicate function a more meaningful nameKrzysztof Parzyszek2016-11-141-16/+16
| | | | | | | Change "orisadd" to "IsOrAdd" to follow the naming conventions, and change "isOrAdd" in the C++ code to "isOrEquivalentToAdd". llvm-svn: 286886
* [Hexagon] Separate Hexagon subreg indices for different register classesKrzysztof Parzyszek2016-11-091-20/+18
| | | | | | | | | | | For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
* [Hexagon] Eliminate Insert4 pseudo-instruction, use combines insteadKrzysztof Parzyszek2016-11-091-1/+2
| | | | llvm-svn: 286368
* Reapply r286080 with a phony change in Hexagon's CMakeLists.txtKrzysztof Parzyszek2016-11-061-20/+106
| | | | | | | | Cmake has not recognized that Hexagon.td has a new dependency in HexagonPatterns.td. All changes to that file were not visible to the build bots. llvm-svn: 286084
* Revert r286080: it breaks build botsKrzysztof Parzyszek2016-11-061-97/+20
| | | | llvm-svn: 286081
* [Hexagon] Remove redundant custom selection codeKrzysztof Parzyszek2016-11-061-20/+97
| | | | | | | | | | | | | | | | The clr/set/toggle-bit instructions (with the bit index given as an immediate operand) had both, custom selection code that generated them, and selection patterns at the same time. The selection patterns were not used, because the custom selection code was executed first. This patch removes the custom code in favor of the selection patterns. The custom code handled 64-bit registers as well with an immediate bit index, and so new patterns were added to implement that. It was also the same case for the instruction "Rd += asr(Rs, Rt)", except that the custom code did not offer any additional functionality, and was simply removed. llvm-svn: 286080
* [Hexagon] Round 5 of selection pattern simplificationsKrzysztof Parzyszek2016-11-061-85/+53
| | | | | | Remove unnecessary type casts in patterns. llvm-svn: 286079
* [Hexagon] Round 4 of selection pattern simplificationsKrzysztof Parzyszek2016-11-061-92/+74
| | | | | | Give simpler or more meaningful names to pat frags and xforms. llvm-svn: 286078
* [Hexagon] Round 3 of selection pattern simplificationsKrzysztof Parzyszek2016-11-061-61/+67
| | | | | | | Remove unnecessary C++ functions for SDNode transforms. Move more pat frags to files where they are used. llvm-svn: 286077
* [Hexagon] Round 2 of selection pattern simplificationsKrzysztof Parzyszek2016-11-061-27/+29
| | | | | | Add pat frags for any-, sign-, and zero-extensions. llvm-svn: 286076
* [Hexagon] Relocate pattern-related bits to proper placesKrzysztof Parzyszek2016-11-051-6/+37
| | | | llvm-svn: 286049
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