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path: root/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
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* Use MCRegister in copyPhysRegMatt Arsenault2019-11-111-1/+1
* Remove the AliasAnalysis argument in function areMemAccessesTriviallyDisjointChangpeng Fang2019-09-261-2/+1
* [MachinePipeliner] Improve the TargetInstrInfo API analyzeLoop/reduceLoopCountJames Molloy2019-09-211-15/+4
* Revert "[MachinePipeliner] Improve the TargetInstrInfo API analyzeLoop/reduce...Mitch Phillips2019-09-201-4/+15
* [MachinePipeliner] Improve the TargetInstrInfo API analyzeLoop/reduceLoopCountJames Molloy2019-09-201-15/+4
* [PowerPC] Enable MachinePipeliner for P9 with -ppc-enable-pipelinerJinsong Ji2019-06-111-1/+1
* MC: Allow getMaxInstLength to depend on the subtargetMatt Arsenault2019-05-221-2/+4
* [CodeGen] Add "const" to MachineInstr::mayAliasBjorn Pettersson2019-04-191-2/+4
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operandFrancis Visoiu Mistrih2018-11-281-5/+5
* Remove FrameAccess struct from hasLoadFromStackSlotSander de Smalen2018-09-051-2/+2
* Extend hasStoreToStackSlot with list of FI accesses.Sander de Smalen2018-09-031-6/+6
* [Hexagon] Expand vgather pseudos during packetizationKrzysztof Parzyszek2018-08-171-0/+2
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-1/+1
* [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to Code...Craig Topper2018-03-291-1/+1
* Fix layering by moving ValueTypes.h from CodeGen to IRDavid Blaikie2018-03-231-1/+1
* Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie2018-03-231-1/+1
* [Hexagon] Make findLoopInstr member of HexagonInstrInfoKrzysztof Parzyszek2018-03-231-0/+4
* [Hexagon] Implement hasLoadFromStackSlot and hasStoreToStackSlotKrzysztof Parzyszek2018-01-231-0/+14
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-01-221-2/+2
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-111-3/+12
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
* [Hexagon] Give uniform names to functions changing addressing modes, NFCKrzysztof Parzyszek2017-10-051-5/+27
* [Hexagon] Add a member Subtarget to HexagonInstrInfo, NFCKrzysztof Parzyszek2017-10-041-0/+1
* [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; ot...Eugene Zelenko2017-09-281-7/+7
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-6/+3
* [Hexagon] Handle Hexagon-specific machine operand target flags in MIRKrzysztof Parzyszek2017-07-101-0/+21
* [Hexagon] Fix dependence check in the packetizerKrzysztof Parzyszek2017-06-011-5/+0
* [Hexagon] Use automatically-generated scheduling information for HVXKrzysztof Parzyszek2017-05-031-1/+14
* [Hexagon] Implement undoing .cur instructions in packetizerKrzysztof Parzyszek2017-05-031-0/+1
* [Hexagon] Remove unused validSubtarget TSFlagsKrzysztof Parzyszek2017-05-021-1/+0
* [Hexagon] Pick a dot-old instruction that matches the architectureKrzysztof Parzyszek2017-03-061-1/+1
* Make TargetInstrInfo::isPredicable take a const reference, NFCKrzysztof Parzyszek2017-03-031-1/+1
* [Hexagon, TableGen] Fix some Clang-tidy modernize and Include What You Use wa...Eugene Zelenko2017-01-041-8/+11
* Finish renaming remaining analyzeBranch functionsMatt Arsenault2016-09-141-3/+3
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-141-2/+2
* AArch64: Use TTI branch functions in branch relaxationMatt Arsenault2016-09-141-2/+4
* [NFC] Remove unnecessary commentDean Michael Berris2016-09-011-4/+2
* [XRay][NFC] Promote isTailCall() as virtual in TargetInstrInfo.Dean Michael Berris2016-09-011-1/+4
* [Hexagon] Allow non-returning calls in hardware loopsKrzysztof Parzyszek2016-08-111-0/+1
* Replace MachineInstr* with MachineInstr& in TargetInstrInfo, NFCKrzysztof Parzyszek2016-08-011-4/+4
* [Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFCKrzysztof Parzyszek2016-07-291-94/+96
* MachinePipeliner pass that implements Swing Modulo SchedulingBrendon Cahoon2016-07-291-3/+30
* [Hexagon] Handle instruction latency for 0 or 2 cyclesKrzysztof Parzyszek2016-07-151-0/+4
* Rename AnalyzeBranch* to analyzeBranch*.Jacques Pienaar2016-07-151-4/+4
* [Hexagon] Packetize function call arguments with tail call instructionsKrzysztof Parzyszek2016-07-141-0/+1
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-15/+12
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-4/+3
* [Hexagon] Optimize addressing modes for load/storeKrzysztof Parzyszek2016-04-291-0/+5
* CodeGen: TII: Take MachineInstr& in predicate API, NFCDuncan P. N. Exon Smith2016-02-231-6/+6
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