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path: root/llvm/lib/Target/Hexagon/HexagonInstrFormats.td
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* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [Hexagon] Change instruction type field in TSFlags to 7 bitsKrzysztof Parzyszek2018-12-031-36/+36
| | | | llvm-svn: 348171
* [Hexagon] Remove support for V4Krzysztof Parzyszek2018-10-191-15/+1
| | | | llvm-svn: 344791
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-111-14/+20
| | | | llvm-svn: 320404
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-2/+1
| | | | | | | This removes the duplicate HVX instruction set for the 128-byte mode. Single instruction set now works for both modes (64- and 128-byte). llvm-svn: 313362
* [Hexagon] Make getMemAccessSize return size in bytesKrzysztof Parzyszek2017-09-141-8/+9
| | | | | | | | It used to return the actual field value from the instruction descriptor. There is no reason for that, that value is not interesting in any way and the specifics of its encoding in the descriptor should not be exposed. llvm-svn: 313257
* [Hexagon] Use automatically-generated scheduling information for HVXKrzysztof Parzyszek2017-05-031-160/+4
| | | | | | Patch by Jyotsna Verma. llvm-svn: 302073
* [Hexagon] Remove unused validSubtarget TSFlagsKrzysztof Parzyszek2017-05-021-16/+0
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301952
* [Hexagon] Replace CVI_VM_CUR_LD type with CVI_VM_LDKrzysztof Parzyszek2017-05-011-0/+3
| | | | | | | | A .cur instruction can be identified by checking isCVINew() && mayLoad(). Patch by Colin LeMahieu. llvm-svn: 301829
* [Hexagon] Replace instruction definitions with auto-generated onesKrzysztof Parzyszek2017-02-101-75/+17
| | | | llvm-svn: 294753
* [Hexagon] Update instruction typesKrzysztof Parzyszek2017-02-071-14/+38
| | | | | | | | | Remove TypeXTYPE, TypeALU32, TypeSYSTEM, TypeJR, and instead use their architecture counterparts. Patch by Colin LeMahieu. llvm-svn: 294321
* [Hexagon] Update MCTargetDescKrzysztof Parzyszek2017-02-061-31/+32
| | | | | | | | | | Changes include: - Updates to the instruction descriptor flags. - Improvements to the packet shuffler and checker. - Updates to the handling of certain relocations. - Better handling of duplex instructions. llvm-svn: 294226
* Fix spelling mistakes in Hexagon target comments. NFC.Simon Pilgrim2016-11-171-1/+1
| | | | | | Identified by Pedro Giffuni in PR27636. llvm-svn: 287248
* [Hexagon] Adding change of flow max 1 (cofMax1) TS flag for marking this ↵Colin LeMahieu2016-10-081-0/+3
| | | | | | restriction rather than implying it from TypeJR. llvm-svn: 283665
* [Hexagon] Update instruction itinerariesKrzysztof Parzyszek2016-07-151-10/+4
| | | | llvm-svn: 275578
* [Hexagon] Remove the remnants of isConstExtProfitableKrzysztof Parzyszek2015-10-201-1/+0
| | | | llvm-svn: 250845
* [Hexagon] Adding skeleton of HVX extension instructions.Colin LeMahieu2015-10-171-0/+45
| | | | llvm-svn: 250600
* [Hexagon] Disassembling, printing, and emitting instructions a whole-bundle ↵Colin LeMahieu2015-05-291-2/+0
| | | | | | at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch. llvm-svn: 238556
* [Hexagon] Separating InstHexagon from OpcodeHexagon.Colin LeMahieu2015-03-101-28/+35
| | | | llvm-svn: 231844
* [Hexagon] Removing v2-4 flags. V4 is the minimum supported version.Colin LeMahieu2015-02-091-20/+11
| | | | llvm-svn: 228605
* [Hexagon] Since decoding conflicts have been resolved, isCodeGenOnly = 0 by ↵Colin LeMahieu2015-02-051-1/+0
| | | | | | default and remove explicitly setting it. llvm-svn: 228316
* [Hexagon] Revert change to isCodeGenOnly = 1 in r228080Colin LeMahieu2015-02-041-0/+1
| | | | llvm-svn: 228082
* [Hexagon] Changing some isCodeGenOnly to isAsmParserOnly since we want them ↵Colin LeMahieu2015-02-041-1/+0
| | | | | | to asm parse but not cause decode conflicts. llvm-svn: 228080
* [Hexagon] Reapplying 224775 load words.Colin LeMahieu2014-12-231-0/+1
| | | | llvm-svn: 224786
* [Hexagon] Adding encodings for JR class instructions. Updating complier usages.Colin LeMahieu2014-12-101-1/+1
| | | | llvm-svn: 223967
* [Hexagon] Adding basic disassembler.Colin LeMahieu2014-10-221-6/+13
| | | | | | | Marking all instructions as CodeGenOnly since encoding bits are not set yet. http://reviews.llvm.org/D5829?vs=on&id=15023&whitespace=ignore-all#toc llvm-svn: 220393
* [Hexagon] Add new InstrItinClass to support timing classes.Jyotsna Verma2014-05-081-52/+53
| | | | | | | This patch doesn't introduce any functionality change. Test cases will be added later when v5 support is added. llvm-svn: 208349
* [Hexagon] Add New TSFlags to be used in the upcoming patches.Jyotsna Verma2014-05-071-22/+40
| | | | llvm-svn: 208239
* Even more spelling fixes for "instruction".Robert Wilhelm2013-09-281-1/+1
| | | | llvm-svn: 191611
* Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.Jyotsna Verma2013-05-101-0/+2
| | | | llvm-svn: 181624
* Hexagon: Set accessSize and addrMode on all load/store instructions.Jyotsna Verma2013-05-071-0/+1
| | | | llvm-svn: 181324
* Hexagon: Change insn class to support instruction encoding.Jyotsna Verma2013-02-141-219/+193
| | | | | | | | This patch doesn't introduce any functionality changes. It adds some new fields to the Hexagon instruction classes and changes their layout to support instruction encoding. llvm-svn: 175205
* Added multiclass for post-increment load instructions.Jyotsna Verma2012-11-141-3/+62
| | | | llvm-svn: 167974
* Use the relationship models infrastructure to add two relations - getPredOpcodePranav Bhandarkar2012-11-011-0/+10
| | | | | | | | | | and getPredNewOpcode. The first relates non predicated instructions with their predicated forms and the second relates predicated instructions with their predicate-new forms. Patch by Jyotsna Verma! llvm-svn: 167243
* Hexagon V5 FP Support.Sirish Pande2012-05-101-2/+2
| | | | llvm-svn: 156568
* Extensions of Hexagon V4 instructions.Sirish Pande2012-05-031-28/+108
| | | | | | This adds new instructions for Hexagon V4 architecture. llvm-svn: 156071
* Revert r155365, r155366, and r155367. All three of these have regressionChandler Carruth2012-04-231-99/+22
| | | | | | | | | | | test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. llvm-svn: 155372
* Hexagon V5 (floating point) support.Sirish Pande2012-04-231-2/+2
| | | | llvm-svn: 155367
* Support for Hexagon VLIW Packetizer.Sirish Pande2012-04-231-22/+99
| | | | llvm-svn: 155365
* This reverts a long string of commits to the Hexagon backend. TheseChandler Carruth2012-04-181-74/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commits have had several major issues pointed out in review, and those issues are not being addressed in a timely fashion. Furthermore, this was all committed leading up to the v3.1 branch, and we don't need piles of code with outstanding issues in the branch. It is possible that not all of these commits were necessary to revert to get us back to a green state, but I'm going to let the Hexagon maintainer sort that out. They can recommit, in order, after addressing the feedback. Reverted commits, with some notes: Primary commit r154616: HexagonPacketizer - There are lots of review comments here. This is the primary reason for reverting. In particular, it introduced large amount of warnings due to a bad construct in tablegen. - Follow-up commits that should be folded back into this when reposting: - r154622: CMake fixes - r154660: Fix numerous build warnings in release builds. - Please don't resubmit this until the three commits above are included, and the issues in review addressed. Primary commit r154695: Pass to replace transfer/copy ... - Reverted to minimize merge conflicts. I'm not aware of specific issues with this patch. Primary commit r154703: New Value Jump. - Primarily reverted due to merge conflicts. - Follow-up commits that should be folded back into this when reposting: - r154703: Remove iostream usage - r154758: Fix CMake builds - r154759: Fix build warnings in release builds - Please incorporate these fixes and and review feedback before resubmitting. Primary commit r154829: Hexagon V5 (floating point) support. - Primarily reverted due to merge conflicts. - Follow-up commits that should be folded back into this when reposting: - r154841: Remove unused variable (fixing build warnings) There are also accompanying Clang commits that will be reverted for consistency. llvm-svn: 155047
* Hexagon V5 (Floating Point) Support.Sirish Pande2012-04-161-2/+2
| | | | llvm-svn: 154829
* HexagonPacketizer patch.Sirish Pande2012-04-121-22/+74
| | | | llvm-svn: 154616
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-8/+8
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Use TSFlag bit to describe instruction properties.Brendon Cahoon2012-02-081-6/+20
| | | | | | | | Creating the isPredicated TSFlag enables the code to use the property defined in the instruction format instead of using a large switch statement. llvm-svn: 150078
* Hexagon backend supportTony Linthicum2011-12-121-0/+242
llvm-svn: 146412
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